cyv15g0204trb Cypress Semiconductor Corporation., cyv15g0204trb Datasheet - Page 11

• Manufacturer Part Number: cyv15g0204trb
• Description: Independent Clock Hotlink Ii Dual Serializer And Dual Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02101 Rev. *B
Pin Definitions
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer
DATA[6:0]
RXRATE[C..D]
SDASEL[2..1][C..D]
[1:0]
TXCKSEL[A..B]
TXRATE[A..B]
TRGRATE[C..D]
RXPLLPD[C..D]
RXBIST[C..D][1:0]
TXBIST[A..B]
TOE2[A..B]
TOE1[A..B]
ROE2[C..D]
ROE1[C..D]
PABRSTB[A..B]
SCANEN2
TMEN3
TOUTA1±
TOUTB1±
TOUTA2±
TOUTB2±
ROUTC1±
ROUTD1±
ROUTC2±
ROUTD2±
INC1±
IND1±
INC2±
IND2±
Note:
6.
Name
Internal Device Configuration Latches
Factory Test Modes
Analog I/O
See Device Configuration and Control Interface for detailed information on the internal latches.
(continued)
Internal Latch
Internal Latch
Internal Latch
LVTTL input
asynchronous,
internal pull-up
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
LVTTL input,
internal pull-down
LVTTL input,
internal pull-down
CML Differential
Output
CML Differential
Output
CML Differential
Output
CML Differential
Output
Differential Input
Differential Input
I/O Characteristics Signal Description
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Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[6:0] bus into the latch
specified by address location on the ADDR[3:0] bus.
latches within the device, and the initialization value of the latches upon the assertion
of RESET. Table 5 shows how the latches are mapped in the device.
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Transmit Clock Select.
Transmit PLL Clock Rate Select.
Reclocker Output PLL Clock Rate Select.
Receive Channel Power Control.
Receive Bist Disabled.
Transmit Bist Disabled.
Transmitter Differential Serial Output Driver 2 Enable.
Transmitter Differential Serial Output Driver 1 Enable.
Reclocker Differential Serial Output Driver 2 Enable.
Reclocker Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer Reset.
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
Transmitter Primary Differential Serial Data Output. The transmitter TOUTx1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-
coupled for PECL-compatible connections.
Transmitter Secondary Differential Serial Data Output. The transmitter TOUTx2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
Reclocker Primary Differential Serial Data Output. The reclocker ROUTx1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-
coupled for PECL-compatible connections.
Reclocker Secondary Differential Serial Data Output. The reclocker ROUTx2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
Primary Differential Serial Data Input. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELx = HIGH.
Secondary Differential Serial Data Input. The INx2± input accepts the serial data
stream for deserialization. The INx2± serial stream is passed to the receiver CDR
circuit to extract the data content when INSELx = LOW.
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CYV15G0204TRB
Table 4 lists the configuration
Page 11 of 30
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