w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 77

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

8.7.4
8.7.5
This register shows the bottom byte of frame status FIFO.
BIT 5:
Bit 4:
Bit 3~2:
Bit 1:
Bit 0:
Reset Value
Reset Value
IRCFG1
FS_FO
REG.
REG.
Bit 7:
Bit 6:
Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)
Set5.Reg5 - Frame Status FIFO Register (FS_FO)
Reserved, write 0.
FSF_TH - Frame Status FIFO Threshold
Set this bit to determine the frame status FIFO threshold level and to generate the FSF_I.
The threshold level values are defined as follows.
FEND_MD - FRAME END MODE
A write to 1 enables hardware to split data stream into equal length frame automatically
as defined in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Reserved, write 0.
IRHSSL - Infrared Handshake Status Select
When set to 0, the HSR (Handshake Status Register) operates the same as defined in IR
mode. A write to 1 will disable HSR, and reading HSR returns 30H.
IR_FULL - Infrared Full Duplex Operation
When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate
in full duplex.
FSFDR
BIT 7
BIT 7
0
0
-
FSF_TH
FSF_TH
LST_FR
BIT 6
BIT 6
0
1
0
0
FEND_M AUX_RX
BIT 5
BIT 5
0
0
-
MX_LEX PHY_ERR
BIT 4
BIT 4
- 77 -
STATUS FIFO THRESHOLD LEVEL
0
0
W83L517D/W83L517D-F
BIT 3
BIT 3
0
0
-
Publication Release Date: May 23, 2005
2
4
CRC_ER
BIT 2
BIT 2
R
0
0
-
IRHSSL
RX_OV
BIT 1
BIT 1
0
0
Revision 1.0
IR_FULL
FSF_OV
BIT 0
BIT 0
0
0