w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 52
w83l517g
Manufacturer Part Number
w83l517g
Description
Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W83L517G.pdf
(133 pages)
- Current page: 52 of 133
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7.2.6
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
Bit 7, 6:
Bit 5, 4:
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
out interrupt is pending.
Bit 2, 1:
below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to a logical 0.
Interrupt Status Register (ISR) (Read only)
These two bits are set to a logical 1 when UFR bit 0 = 1.
These two bits are always logic 0.
These two bits identify the priority level of the pending interrupt, as shown in the table
7
6
0
5
4
0
3
2
- 52 -
1
W83L517D/W83L517D-F
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
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