w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 61

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

Legacy IR:
This register is used to control FIFO functions of the IR.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes and there are more than 4 data characters in the receiver
FIFO, the interrupt will be activated to notify CPU to read the data from FIFO.
Bit 4, 5:
Bit 3:
mode 1 if UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to its initial state. This bit will be
cleared to logical 0 by itself after being set to logical 1.
Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit will be
cleared to a logical 0 by itself after being set to logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the IR. This bit should be set to logical 1 before
other bits of UFR can be programmed.
Advanced IR:
Advanced IR
BIT 7, 6:
Legacy IR
Reset Value
MODE
BIT 7
0
0
1
1
Its definition is the same as Legacy IR. RXTH_I becomes 1 when the Receiver FIFO
Threshold Level is equal to or larger than the defined value shown as follow.
Reserved
When this bit is programmed to logic 1, the DMA mode will change from mode 0 to
RXFTL1
RXFTL1
(MSB)
(MSB)
BIT 7
0
BIT 6
0
1
0
1
RXFTL0
RXFTL0
(LSB)
(LSB)
BIT 6
RXFTL1, 0 – RECEIVER FIFO THRESHOLD LEVEL
0
IR FIFO Control Register (UFR):
TABLE: FIFO TRIGGER LEVEL
TXFTL1
(MSB)
BIT 5
0
0
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
TXFTL0
- 61 -
(LSB)
BIT 4
0
0
W83L517D/W83L517D-F
BIT 3
0
0
0
Publication Release Date: May 23, 2005
01
04
08
14
TXF_RST RXF_RST EN_FIFO
TXF_RST RXF_RST EN_FIFO
BIT 2
0
BIT 1
0
Revision 1.0
BIT 0
0