uja1076tw/5v0/wd NXP Semiconductors, uja1076tw/5v0/wd Datasheet - Page 23

• Manufacturer Part Number: uja1076tw/5v0/wd
• Description: High-speed Can Core System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1076_1
Product data sheet
mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and
enter Standby mode. The status of the wake-up pins can be read via the wake-up level
status bits (WLS1 and WLS2) in the WD_and_Status register
Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts
is enabled (WIC1 ≠ 00 or WIC2 ≠ 00).
The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting
bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are
sampled continuously). The sampling will be performed on the rising edge of WBIAS (see
Figure
(WBC) in the Mode_Control register.
Figure 12
Fig 11. Wake-up pin sampling synchronized with WBIAS signal
Fig 12. Typical application for cyclic sampling of wake-up signals
11). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit
Wake-up int
WAKEx pin
WBIAS pin
UJA1076
WBIASI
(internal)
shows typical circuit for implementing cyclic sampling of the wake-up inputs.
GND
BAT
WBIAS
WAKE1
WAKE2
Rev. 01 — 1 December 2009
enable bias
47 kΩ
47 kΩ
PDTA144E
High-speed CAN core system basis chip
disable bias
disable bias
biasing of
switches
sample of
WAKEx
wake level latched
(Table
sample of
WAKEx
4).
UJA1076
© NXP B.V. 2009. All rights reserved.
015aaa078
sample of
WAKEx
015aaa122
23 of 45
t