uja1076tw/5v0/wd NXP Semiconductors, uja1076tw/5v0/wd Datasheet - Page 17

• Manufacturer Part Number: uja1076tw/5v0/wd
• Description: High-speed Can Core System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1076_1
Product data sheet
6.5.1 RSTN pin
6.5.2 EN output
6.5.3 LIMP output
A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least t
the microcontroller (external reset). A reset pulse is output on RSTN by the SBC when a
system reset is triggered internally.
The reset pulse width (t
generated by a V1 undervoltage event (see
(V
selected by connecting a 900 Ω ±10 % resistor between pins RSTN and V1. If a resistor is
not connected, the reset pulse will be long (see
In all other cases (e.g. watchdog-related reset events) the reset pulse length will be short.
The EN pin can be used to control external hardware, such as power components, or as a
general-purpose output when the system is running properly.
In Normal and Standby modes, the microcontroller can set the EN control bit (bit ENC in
the Mode_Control register; see
ENC = 1 and MC = 10 or 11. A reset event will cause pin EN to go LOW. EN pin behavior
is illustrated in
The LIMP pin can be used to enable the so called ‘limp home’ hardware in the event of an
ECU failure. Detectable failure conditions include SBC overtemperature events, loss of
watchdog service, RSTN or V1 clamped LOW and user-initiated or external reset events.
The LIMP pin is a battery-related, active-LOW, open-drain output.
A system reset will cause the limp home warning control bit (bit LHWC in the
Mode_Control register; see
reset is generated, bit LHC will be set which will force the LIMP pin LOW. The application
should clear LHWC after each reset event to ensure the LIMP output is not activated
during normal operation.
In Overtemp mode, bit LHC is always set and, consequently, the LIMP output is always
active. If the application manages to recover from the event that activated the LIMP
output, LHC can be cleared to deactivate the LIMP output.
Fig 5.
BAT
> V
RSTN
mode
ENC
EN
th(det)pon
Behavior of EN pin
Figure
) or Overtemp (temperature < T
STANDBY
Rev. 01 — 1 December 2009
5.
w(rst)
) is selectable (short or long) if the system reset was
Table
Table
5) to be set. If LHWC is already set when the system
5) via the SPI interface. Pin EN will be HIGH when
Section
High-speed CAN core system basis chip
NORMAL
Table
th(rel)otp
6.6.2) or by the SBC leaving Off
10).
) modes. A short reset pulse is
STANDBY
UJA1076
© NXP B.V. 2009. All rights reserved.
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