lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 311

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
REGISTER #
0424h-043Fh
0442h-0450h
041Ch
041Dh
041Ah
041Bh
041Eh
041Fh
0414h
0415h
0416h
0417h
0418h
0419h
0420h
0421h
0422h
0423h
0440h
0441h
0451h
0452h
0453h
0454h
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
MAC_RX_OVRSZE_CNT_MII
MAC_RX_PKTOK_CNT_MII
MAC_RX_PAUSE_CNT_MII
MAC_RX_GOODPKTLEN_CNT_MII
MAC_RX_SYMBL_CNT_MII
MAC_RX_256_TO_511_CNT_MII
MAC_RX_1024_TO_MAX_CNT_MII
MAC_TX_DEFER_CNT_MII
MAC_TX_PAUSE_CNT_MII
MAC_TX_PKTOK_CNT_MII
MAC_RX_ALIGN_CNT_MII
MAC_RX_512_TO_1023_CNT_MII
MAC_RX_CRCERR_CNT_MII
MAC_RX_FRAG_CNT_MII
MAC_RX_MULCST_CNT_MII
MAC_RX_BRDCST_CNT_MII
MAC_TX_FC_SETTINGS_MII
MAC_RX_CTLFRM_CNT_MII
MAC_RX_JABB_CNT_MII
MAC_RX_PKTLEN_CNT_MII
MAC_TX_64_CNT_MII
MAC_TX_CFG_MII
RESERVED
RESERVED
SYMBOL
DATASHEET
Port 0 MAC Receive 256 to 511 Byte Count Register,
Section 14.5.2.7
Port 0 MAC Receive 512 to 1023 Byte Count Register,
Section 14.5.2.8
Port 0 MAC Receive 1024 to Max Byte Count Register,
Section 14.5.2.9
Port 0 MAC Receive Oversize Count Register,
Section 14.5.2.10
Port 0 MAC Receive CRC Error Count Register,
Section 14.5.2.12
Port 0 MAC Receive Multicast Count Register,
Section 14.5.2.13
Port 0 MAC Receive Broadcast Count Register,
Section 14.5.2.14
Port 0 MAC Receive Pause Frame Count Register,
Section 14.5.2.15
Port 0 MAC Receive Fragment Error Count Register,
Section 14.5.2.16
Section 14.5.2.17
Section 14.5.2.18
Port 0 MAC Receive Packet Length Count Register,
Section 14.5.2.19
Port 0 MAC Receive Good Packet Length Count Register,
Section 14.5.2.20
Port 0 MAC Receive Symbol Error Count Register,
Section 14.5.2.21
Port 0 MAC Receive Control Frame Count Register,
Section 14.5.2.22
Port 0 MAC Transmit Configuration Register,
Port 0 MAC Transmit Flow Control Settings Register,
Section 14.5.2.24
Port 0 MAC Transmit Deferred Count Register,
Section 14.5.2.25
Port 0 MAC Transmit Pause Count Register,
Port 0 MAC Transmit OK Count Register,
Port 0 MAC Transmit 64 Byte Count Register,
Port 0 MAC Receive OK Count Register,
Port 0 MAC Receive Jabber Error Count Register,
Port 0 MAC Receive Alignment Error Count Register,
Reserved for Future Use
Reserved for Future Use
311
REGISTER NAME
Section 14.5.2.11
Section 14.5.2.27
Revision 1.2 (04-08-08)
Section 14.5.2.23
Section 14.5.2.26
Section 14.5.2.28