lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 144

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
10.2.2.5
A
C
K
D
7
D
6
Data Byte
D
5
Data Cycle
D
4
Sequential reads are used by the EEPROM Loader. Refer to
additional information.
For a register level description of a read operation, refer to
Operation," on page
I
Following the device addressing, a data byte may be written to the EEPROM by outputting the data
after receiving the acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM
slave and the I
send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the
Command Register (E2P_CMD)
Following the data byte write cycle, the I
write is finished. A start condition is sent followed by a control byte with a control code of 1010b,
chip/block select bits low, and the R/~W bit low. If the EEPROM is finished with the byte write, it will
respond with an acknowledge. Otherwise, it will respond with a no-acknowledge and the I
will repeat the poll. If the acknowledge does not occur within 30mS, a time-out occurs. Once the I
master receives the acknowledge, it concludes by sending a start condition, followed by a stop
condition, which will place the EEPROM into standby.
Figure 10.4
D
3
For a register level description of a write operation, refer to
Operation," on page
2
C EEPROM Byte Writes
D
2
D
1
D
0
C
A
K
illustrates typical I
P
2
S 1 0 1 0
C master finishes the write cycle with a stop condition. If the EEPROM slave fails to
139.
139.
Control Byte
Poll Cycle
Chip / Block
Select Bits
Figure 10.6 I
0 0 0
2
C EEPROM byte write.
is set.
DATASHEET
0
R/~W
2
A
C
K
C EEPROM Byte Write
2
S 1 0 1 0
C master will poll the EEPROM to determine when the byte
144
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Control Byte
Poll Cycle
Chip / Block
Select Bits
0 0 0
0
R/~W
Section 10.2.4, "EEPROM Loader"
Section 10.2.1, "EEPROM Controller
Section 10.2.1, "EEPROM Controller
A
C
K
...
S 1 0 1 0
Control Byte
Poll Cycle
Chip / Block
SMSC LAN9311/LAN9311i
Select Bits
0 0 0
0
2
Conclude
R/~W
EEPROM
Datasheet
C master
A
C
K
S P
for
2
C