z85230 ZiLOG Semiconductor, z85230 Datasheet - Page 78

• Manufacturer Part Number: z85230
• Description: Enhanced Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

PS005303-0907
Z85230 Read Cycle Timing
Z85230 Write Cycle Timing
A/B, D/C
from the falling edge of WR or RD in the first transaction involving the ESCC, to the fall-
ing edge of WR or RD in the second transaction. This time must be at least four PCLKs
regardless of which register or channel is accessed.
Figure 20
INTACK must remain stable throughout the cycle. The effective RD time reduces if CE
falls after RD falls, or if it rises before RD rises.
Figure 21
status on INTACK must remain stable throughout the cycle. The effective WR time
reduces if CE falls after WR falls, or if it rises before WR rises. In Write Cycle timing, the
WR signal returns a High slightly before the Address goes invalid.
Because many popular CPUs do not guarantee that the databus is valid when WR is Low,
the ESCC no longer requires a valid databus when the WR pin is Low. For more informa-
tion, see AC characteristics parameter 29 available in
INTACK
D7–D0
RD
CE
illustrates Read Cycle timing. Addresses on A/B and D/C and the status on
on page 74 illustrates Write Cycle timing. Addresses on A/B and D/C and the
Figure 20. Read Cycle Timing (Z85230)
Address Valid
Data Valid
Table
46.
Product Specification
Z80230 Interface Timing
Z85230/Z80230
73