z85230 ZiLOG Semiconductor, z85230 Datasheet - Page 34

• Manufacturer Part Number: z85230
• Description: Enhanced Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

PS005303-0907
Notes:
controller to transfer the next frame into memory while the CPU verifies the previously
received frame.
1. All Sent bypasses MUX and equals contents of SCC Status Register.
2. Parity bits bypass MUX and equals contents of SCC Status Register.
3. EOF is set to 1 whenever reading from the FIFO.
Summarizing the operation: data is received, assembled, and loaded into the 8-byte FIFO
before transferring to memory by the DMA controller.
Interface
to SCC
RR1
See Notes:, next.
2 Bits
SCC Status Register
Overrun, CRC Error
Residue Bits (3)
6-Bit MUX
5 Bits
Figure 15. SDLC Frame Status FIFO
6 Bits
RR1
10- by 19- Bits
5 Bits
FIFO Array
RR7 Bit 7
FIFO Overflow Status Bit
(1 on overflow)
EOF=1
Bit Bit
Frame Status FIFO Circuitry
7
RR7 Bit 7
FIFO data-available status bit
(1 during read)
6
Byte Counter
6 Bits
5-0
Bits
RR7 5 - 0 + RR6 7-0
14-Bit Byte Counter
(16 KB Maximum Count)
14 Bits
RR6
8 Bits
EN
Status Read Complete
4-Bit Comparator
Over
Reset on Flag Detect
Increment on
Each Received Character
Enable Count in SDLC
Head Pointer
4-Bit Counter
4-Bit Counter
Tail Pointer
EOF Signal
Z80230/Z85230 Enhancements
Product Specification
Equal
WR15 Bit 2
Set Enables
Status FIFO
Z85230/Z80230
Enable
FIFO
29