z85230 ZiLOG Semiconductor, z85230 Datasheet - Page 32

• Manufacturer Part Number: z85230
• Description: Enhanced Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

PS005303-0907
DPLL Counter Tx Clock Source
Read Register 0 Status Latched During Read Cycle
DPLL CLK
synchronous frame is guaranteed to generate two TBE interrupts even if a Reset Transmit
Buffer Interrupt command for the data created interrupt is issued after the CRC interrupt
occurs (Time A in
if the EOM latch resets before the end of the frame.
When the DPLL is selected as the transmit clock source, the DPLL counter output is the
DPLL source clock divided by the appropriate divisor for the programmed data encoding
format. In FM mode (FM0 or FM1), the DPLL counter output signal is the input frequency
divided by 16.
In NRZI mode, the DPLL counter output signal is the input clock cycle divided by 32.
This feature provides a jitter-free output signal that replaces the DPLL transmit clock out-
put as the transmit clock source. This action has no effect on the use of the DPLL as the
receive clock source (see
The contents of Read Register 0, RR0 is latched during a Read operation. The ESCC pre-
vents the contents of RR0 from changing during a Read operation. But, the SCC allows
the status of RR0 to change while reading the register and may require reading RR0 twice.
The contents of RR0 is updated after the rising edge of RD signal.
TxIP Bit
TxBE
Input
Data
Figure
Data
Input Frequency Divided by 16 (FM0 or FM1)
Input Clock Cycle Divided by 32 for NRZI
TxIP 1
Figure 14. DPLL Outputs
Figure 13. TxIP Latching
DPLL Counter
Figure
13). Two
DPLL
CRC1
14).
Reset TBE
CRC2
commands are required. The TxIP latches
DPLL Output to Receiver
DPLL Output to Transmitter
Flag
Time A
TxIP 2
Z80230/Z85230 Enhancements
Product Specification
Z85230/Z80230
27