z85230 ZiLOG Semiconductor, z85230 Datasheet - Page 20

• Manufacturer Part Number: z85230
• Description: Enhanced Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

PS005303-0907
ESCC Data Communications Capabilities
CPU/DMA BLOCK TRANSFER
The ESCC provides a BLOCK TRANSFER mode to accommodate CPU/DMA controller.
The BLOCK TRANSFER mode uses the WAIT/REQUEST output in conjunction with the
WAIT/REQUEST bits in WR1. The WAIT/REQUEST output can be defined as a WAIT
line in the CPU BLOCK TRANSFER mode or as a REQUEST line in the DMA BLOCK
TRANSFER mode.
To a DMA controller, the ESCC REQUEST output indicates that the ESCC is ready to
transfer data to or from memory.
To the CPU, the WAIT line indicates that the ESCC is not ready to transfer data, thereby
requesting the CPU to extend the I/O cycle.
The DTR/REQUEST line allows full-duplex operation under DMA control. The ESCC
can be programmed to deassert the DTR/REQUEST pin with the same timing as the
WAIT/REQUEST pin if WR7’ bit 4 is 1.
The ESCC provides two independent full-duplex programmable channels for use in any
common ASYNCHRONOUS or SYNCHRONOUS data communication protocols (see
Figure
Marking Line
SYNC
Flag
8). The channels have identical features and capabilities.
Address
SYNC
SYNC
Signal
Start
Figure 8. Various ESCC Protocols
Data
Data
Data
Data
Control
Parity
SDLC/HDLC/X.25
External Sync
Asynchronous
Monosync
Stop
Bisync
Data
Information
Data
Data
Data
Data
CRC1
CRC1
CRC1
CRC1
CRC2
CRC2
CRC2
CRC2
Product Specification
Marking Line
Functional Description
Z85230/Z80230
Flag
15