z85230 ZiLOG Semiconductor, z85230 Datasheet - Page 108

• Manufacturer Part Number: z85230
• Description: Enhanced Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

PS005303-0907
Default RR10 Value Problem Description
Default RR10 Value Problem Solution
CRC Problem Description
CRC Problem Solution
D7
C5
C15
D7
C6
C15
RR10 bit 6, the 2 clock missing bit, is sometimes erroneously set to indicate that the DPLL
detects a clock edge in two successive tries after hardware reset.
Ignore the first bit 7 value Read from RR10 after reset.
The CRC can not be interpreted from the Receive FIFO when one or two residue bits are
sent. The CRC value is received and checked correctly but is not loaded to the Receive
FIFO. The two types of CRC problems are described below:
•
The last three bytes of the Receive FIFO read:
Bits 6 and 7 of the CRC are lost.
•
The last three bytes of the Receive FIFO read:
Bit 7 of the CRC is lost.
The CRC is received and loaded into the Receive FIFO in other situations (that is, the 0, 3,
4, 5, 6, and 7 residue bits).
The Residue code, RR1 bits 3, 2, and 1, is reported independently of the number of residue
bits sent.
Ignore the CRC value read from the Receive FIFO if one or two residue bits are sent.
Two Residue bits (Residue code is
One Residue Bit (Residue code is
D6
C4
C14
D6
C5
C14
D5
C3
C13
D5
C4
C13
D4
C2
C12
D4
C3
C12
D3
C1
C11
D3
C2
C11
111
000
)
)
D2
C0
C10
D2
C1
C10
D1
D9
C9
D1
C0
C9
Product Specification
D0
D8
C8
D0
D8
C8
Z80230/Z85230 Errata
Z85230/Z80230
103