isp1512a NXP Semiconductors, isp1512a Datasheet - Page 30

• Manufacturer Part Number: isp1512a
• Description: Ulpi Hi-speed Usb Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 30.
Table 31.
Table 32.
Table 33.
ISP1512A_1
Preliminary data sheet
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Symbol
-
SESS_END_L
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description
DEBUG - Debug register (address R = 15h) bit allocation
DEBUG - Debug register (address R = 15h) bit description
10.11 USB_INTR_L register
10.12 DEBUG register
Symbol
-
LINESTATE1
LINESTATE0
R
R
7
0
7
0
The bits of the USB_INTR_L register are automatically set by the ISP1512A when an
unmasked change occurs on the corresponding interrupt source signal. The ISP1512A
will automatically clear all bits when the link reads this register, or when the PHY enters
low-power mode.
Remark: It is optional for the link to read this register when the clock is running because
all signal information will automatically be sent to the link through the RXCMD byte.
The bit allocation of this register is given in
The bit allocation of the DEBUG register is given in
current value of signals useful for debugging.
Description
reserved
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
V
Cleared when this register is read.
Host Disconnect Latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
R
R
6
0
6
0
BUS
reserved
Description
reserved
Line State 1: Contains the current value of LINESTATE 1
Line State 0: Contains the current value of LINESTATE 0
Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.
R
R
5
0
5
0
reserved
Rev. 01 — 31 July 2008
R
R
4
0
4
0
SESS_
END_L
Table
R
R
3
0
3
0
30.
Table
VALID_L
SESS_
R
R
2
0
32. This register indicates the
2
0
ULPI HS USB transceiver
VALID_L
STATE1
VBUS_
LINE
ISP1512A
R
R
1
0
1
0
© NXP B.V. 2008. All rights reserved.
DISCON_L
STATE0
HOST_
LINE
R
R
0
0
0
0
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