ucb1500 NXP Semiconductors, ucb1500 Datasheet - Page 4

• Manufacturer Part Number: ucb1500
• Description: Pci To Ac97 Bridge/host Controller
• Manufacturer: NXP Semiconductors

Table 2:
[1]
[2]
Philips Semiconductors
9397 750 07443
Product specification
Symbol
IRDY
TRDY
DEVSEL
STOP
IDSEL
AD[31:0]
CBE[3:0]
PAR
INTA
PME
SERR
PERR
CLKRUN
AC link controller interface
BITCLK
SDATAIN[1:0]
SDATAOUT
SYNC
AC97_RST
Serial EEPROM interface
EEPCLK
EEPD
Power management; miscellaneous
V
TEST
Power pins
V
V
V
AUX
DD
SS
AUX
S/T/S: Sustained 3-State is an active-LOW 3-state signal owned and driven by one agent at a time. The agent that drives an S/T/S pin
LOW must drive it HIGH for at least one clock before letting it float. A new agent cannot start driving a S/T/S signal any sooner than one
clock after the previous owner 3-states it.
O/D: Open Drain allows multiple devices to share as a wired OR.
_AV
Pin description
Pin
30
31
33
34
15
4, 5, 7, 8, 9, 10, 12,
13, 17, 18, 19, 20,
23, 24, 25, 26,41,
42, 44, 45, 46, 47,
49, 50, 52, 54, 55,
56, 57, 59, 60, 62
14, 28, 39, 51
38
77
63
36
35
78
75
65. 64
70
71
66
73
74
69
79
1, 11, 22, 27, 37,
43, 53, 61
6, 16, 21, 32, 40,
48, 58, 72, 76
67
…continued
Type
S/T/S
S/T/S
S/T/S
S/T/S
I
T/S
T/S
T/S
O/D
O/D
O/D
S/T/S
S/T/S
I
I
O
O
O
O
I/O
I
I
S
S
S
[2]
Description
PCI IRDY, input during slave, output during master.
PCI TRDY, output during slave, input during master.
PCI DEVSEL, output during slave, input during master.
PCI STOP, output during slave, input during master.
PCI IDSEL signal.
PCI address/data.
PCI command/byte-enable, input during slave, output during master.
PCI parity.
PCI interrupt.
Open drain, V
pins are V
PCI system error
PCI parity error
Primary PCI bus clock run. Used by the central resource to stop the PCI
clock or to slow it down
Serial data clock; or input for secondary codecs.
Input from AC97/MC97 codecs. V
Output to AC97/MC97 codecs. Driven to 0 at power-up or when RST
asserted.
AC97 sync. Driven to 0 at power-up or when RST asserted.
AC97 reset. Driven to 0 at power-up or when RST asserted. V
EEPROM clock.
EEPROM serial data port.
Auxiliary power available, V
Test mode.
3.3 V power pins.
Ground pins.
Auxiliary power. If auxiliary power is not available or not necessary, this pin
must be connected to V
slave mode: output only during data read phase.
master mode: output during address phase and data write phase.
Rev. 03 — 7 July 2000
AUX
AUX
powered and can trigger PME.
powered PCI power management pin. SDA TAIN[1:0]
DD
.
AUX
powered.
AUX
PCI to AC97 bridge/host controller
powered and can trigger PME.
© Philips Electronics N.V. 2000. All rights reserved.
UCB1500
AUX
powered.
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