ucb1500 NXP Semiconductors, ucb1500 Datasheet - Page 21

• Manufacturer Part Number: ucb1500
• Description: Pci To Ac97 Bridge/host Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 07443
Product specification
8.1.3 [0011]: Receive DMA #1 Descriptor table pointer (DTP) register
8.1.4 [0012]: Receive DMA #1 FIFO count register
8.1.5 [0013]: Receive DMA #1 command register
Table 25: Receive DMA #1 DPT register bit description
Table 26: Receive DMA #1 FIFO count register bit description
Table 27: Receive DMA #1 Command Register bit description
Bit
15-0
Bit
15(r)
14
13-7
6-0(r)
Bit
15-14
13
12(r)
Description
Descriptor Table Pointer [31:16]
Bits 31-16 of receive DMA #1 Descriptor Table Pointer.
Description
Open PCI Master Cycle
(For internal use only): This bit is set if there is an outstanding PCI master cycle
as a result of PCI retry termination by the target. Software should wait for this bit
to be cleared when initiating another DMA transfer right after an aborted DMA
transfer.
DTP Invalid Bit Mask
If this bit is set to ‘1’, the receive DMA engine will not stop even if the current
descriptor fetched has the invalid bit set.
Reserved.
Receive DMA #1 FIFO count
(For internal use only) number of received bytes that is still in the internal 64-byte
FIFO.
Description
Threshold level
Specifies the level at which data is transferred from the 64-byte FIFO to main
memory. Recommended setting is for at least 16 bytes threshold.
Buffer Overrun auto recovery (for internal user only)
If set, UCB1500 will automatically recover from buffer overrun without user
intervention. Upon detecting an overrun condition, UCB1500 will clear the invalid
bit of the current descriptor, flush the internal FIFO, and then resume the DMA
cycle. UCB1500 keeps track of the number of DMA errors caused by buffer
overrun and will generate the auto recovery cycle until the count reaches 15h at
which time the DMA cycle is aborted.
Receive DMA #1 Abort status
This read-only bit is set if the receive channel has been aborted as a result of a
PCI abort or a software abort or a DMA error. The condition is cleared by writing
a ‘1’ to the receive DMA clear abort bit, bit 5 of this register.
00 = 4 bytes, data will be transferred to memory as soon as there is at least
4 bytes of receive data in the receive FIFO
01 = 16 bytes
10 = 32 bytes
11 = 48 bytes
Rev. 03 — 7 July 2000
PCI to AC97 bridge/host controller
© Philips Electronics N.V. 2000. All rights reserved.
UCB1500
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