gc80c521a CORERIVER Semiconductor, gc80c521a Datasheet - Page 69

• Manufacturer Part Number: gc80c521a
• Description: Flash / Isp / Iap 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

SPIDR (B6h) : SPI TX / RX Data
SPICON (B4h) : SPI Control
6.13. SPI : SFR
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Eight Programmable Bit Rates
Clock Polarity & Phase Selection
Support Write Collision Protection
Wake-up from IDLE mode
DATA7
[0] : 4-wire mode
[1] : First LSB, Last MSB
[1] : SPI Master Mode
[0,0] : Leading edge Rising, Leading edge Sampling
[0,1] : Leading edge Rising, Trailing edge Sampling
[1,0] : Leading edge Falling, Leading edge Sampling
[1,1] : Leading edge Falling, Trailing edge Sampling
[1] : SPI Output Enable
[1] : SPI Enable
-
MODE
BORD
MSSEL
CKPOL, CKPHA : SPI clock Polarity & Phase
SPIOEN
SPIEN
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
DATA6
MODE
: SPI mode selection
: SPI Transfer Bit Order
: SPI Master / Slave Selection Flag
: SPI Output Enable
: SPI Enable Flag
DATA5
BORD
DATA4
MSSEL
Register
DATA3
CKPOL
[1] : 3-wire mode
[0] : First MSB, Last LSB
[0] : SPI Slave Mode
[0] : SPI Output Disable
[0] : SPI Disable
Register
DATA2
CKPHA SPIOEN
DATA1
DATA0
SPIEN
SPIST (C0h) : SPI Status
EIE (A1h) : Extended Interrupt Enable Register
SPICK (B5h) : SPI Clock Control
R/W(0)
ESPI
[1] : Set by H/W when user write SPIDR while SPI is enabled.
[0] : Cleared by H/W when the data is moved to TX shift register
[1] : Serial transfer is complete. If SPIE is set and EA is set, SPI
[1] : SPIDR is written when TXBV is set. The previous data is lost.
[1] : If a new data is received while SPIDR is still holding
the previous data, the flag is set.
SPIF must be cleared before receiving a data again.
[0,0,0] : Fosc / 2
[0,1,0] : Fosc / 8
[1,0,0] : Fosc / 32
[1,1,0] : Fosc / 128
-
TXBV
SPIF
SPICOL
SPIOF
-
ESPI
SPICK[2:0]
interrupt is generated.
or SPI is disabled.
-
-
-
: TX buffer of SPIDR holds valid data.
: SPI Interrupt Flag
: SPI Write Collision Flag
: SPI Read Overflow Flag
: SPI Interrupt Enable
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
EI2C
: SPI Master Clock Divider
-
-
MiDAS1.0B Family
EWDT
Register
-
-
TXBV
R(0)
EX5
Register
[0,0,1] : Fosc / 4
[0,1,1] : Fosc / 16
[1,0,1] : Fosc / 64
[1,1,1] : Fosc / 256
-
R/W(0) R/W(0) R/W(0)
SPICK2 SPICK1 SPICK0
R/W(0) R/W(0) R/W(0)
SPIF
EX4
SPICOL
EX3
SPIOF
EX2
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