gc80c521a CORERIVER Semiconductor, gc80c521a Datasheet - Page 144

• Manufacturer Part Number: gc80c521a
• Description: Flash / Isp / Iap 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

[0] : 2nd Byte SLA Match Disable [1] : 2nd SLA Byte Match Enable
[0] : Hold SCL ‘low’. The flag is cleared automatically by H/W
[1] : Release SCL ‘float’. The flag is set by S/W
[0] : Send Acknowledge after last byte
[1] : Send Not Acknowledge after last byte
In Master Receiver mode, before receiving last byte, the flag must be
set.
[0] : Start or Idle state.
The flag is cleared automatically after Stop bit in Master mode
and when I2CEN is cleared.
[0] : Stop or Idle state
If the bus is not free, it waits for Stop bit condition.
The flag is cleared automatically after Start bit in Master mode
and when I2CEN is cleared.
[0] : Disable I2C IO
[0] : Disable I2C module
I2CCON
Appendix B :
-
SLA2ME : 2nd Byte Slave Address Match Enable in Slave mode
SCLHD
LASTB
PGEN
SGEN
I2CIOEN : Enable I2C IO
I2CEN
SLA2ME SCLHD
R/W(0) R/W(1) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
(E9h) : I2C Control Register
: Hold SCL ‘low’ for Wait State in Slave mode.
: Indicate last byte in Master Receiver mode.
: Generate Stop bit.
: Generate Start bit
: Enable I2C module
LASTB
PGEN
[1] : Generate Stop bit.
[1] : Generate Start bit
[1] : Enable I2C IO
[1] : Enable I2C module
SFR Description [E9h ~ ECh]
SGEN
I2CIOEN I2CEN
MDAT.7 MDAT.6 MDAT.5 MDAT.4 MDAT.3 MDAT.2 MDAT.1 MDAT.0
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
MSCL.7 MSCL.6 MSCL.5 MSCL.4 MSCL.3 MSCL.2 MSCL.1 MSCL.0
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
SLA1.7
In 7-bit address mode and in 10-bit address mode (1st SLA),
In 10-bit address mode (2nd SLA),
[0] : Slave mode
[0] : 7-bit mode
[0] : Start/Stop Interrupt Disable [1] : Start/Stop Interrupt Enable
[1] : Respond to the general call address (0x00)
I2CCFG
I2CSLA
I2CDAT
I2CSCL
I2C_SLA[7:1] is used for matching address and I2C_SLA[0] is masked.
I2C_SLA[7:0] is used for matching address.
-
MSSEL
ADSEL
SP_IE
GCE
SLA[7:0]
SLA1.6
-
(EBh) : I2C Slave Address Register
(EDh) : I2C SCL Clock Scaler
(EAh) : I2C Configuration Register
(ECh) : I2C Address / Data Register
: I2C Master/Slave Mode Selection
: 7-bit / 10-bit Address Mode Selection in Slave mode
: Start/Stop Interrupt Enable
: General Call Enable in Slave mode
: I2C Slave Address Register.
SLA1.5
-
(18/19)
SLA1.4
MiDAS1.0B Family
-
R/W(0) R/W(0) R/W(0) R/W(0)
MSSEL
SLA1.3
[1] : Master mode
[1] : 10-bit mode
ADSEL
SLA1.2
SLA1.1
SP_IE
SLA1.0
GCE
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