gc80c521a CORERIVER Semiconductor, gc80c521a Datasheet - Page 59

• Manufacturer Part Number: gc80c521a
• Description: Flash / Isp / Iap 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

I2CCON (E9h) : I
6.12. I2C : SFR
[0] : Stop or Idle state
[0] : 2
[0] : Hold SCL ‘low’. The flag is cleared automatically by H/W
[1] : Release SCL ‘float’. The flag is set by S/W
[0] : Send Acknowledge after last byte
[1] : Send Not Acknowledge after last byte
In Master Receiver mode, before receiving last byte, the flag must be
set.
[0] : Start or Idle state.
The flag is cleared automatically after Stop bit in Master mode
and when I2CEN is cleared.
If the bus is not free, it waits for Stop bit condition.
The flag is cleared automatically after Start bit in Master mode
and when I2CEN is cleared.
[0] : Disable I2C IO
[0] : Disable I2C module
-
-
SLA2ME
SCLHD
LASTB
PGEN
SGEN
I2CIOEN
I2CEN
nd
SLA2ME SCLHD
R/W(0) R/W(1) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
Byte SLA Match Disable
: 2
: Hold SCL ‘low’ for Wait State in Slave mode.
: Indicate last byte in Master Receiver mode.
: Generate Stop bit.
: Generate Start bit
: Enable I2C IO
: Enable I2C module
nd
2
Byte Slave Address Match Enable in Slave mode
C Control Register
LASTB
PGEN
[1] : 2
[1] : Generate Stop bit.
[1] : Generate Start bit
[1] : Enable I2C IO
[1] : Enable I2C module
(Cont’d)
nd
SGEN
SLA Byte Match Enable
I2CIOEN I2CEN
I2CST (E8h) : I
R/W(0) R/W(0)
I2CIF
[0] : Idle
It is set each time a byte is received or transmitted.
If SP_IE flag in I2C_CFG SFR is set, it is set at Start/Stop condition.
The flag is set by H/W and cleared by S/W.
[0] : Idle
It is set when a byte is received while I2C_BUF SFR is still holding
the previous byte.
It is set by H/W and cleared by S/W
[0] : Indicate receiving Acknowledge bit.
[1] : Indicate receiving Not Acknowledge bit.
[0] : Write state
[0] : Indicates the last byte received or transmitted was Data
[1] : Indicates the last byte received or transmitted was Address
[0] : Indicates Stop bit was not detected.
[1] : Indicates Stop bit was detected.
This flag is cleared when I2CS is set or I2CEN is cleared.
[0] : Indicates Start bit was not detected.
[1] : Indicates Start bit was detected.
This flag is cleared when I2CP is set or I2CEN is cleared.
[0] : RX not complete (Receiver), TX not complete (Transmitter)
[1] : RX complete (Receiver), TX complete (Transmitter)
I2CIF
I2COF
I2CACK
I2CRW
I2CDA
I2CP
I2CS
I2CBF
I2COF
: I
: I2C Overflow Flag in slave & master mode
: I2C Acknowledge flag in slave & master mode.
: I2C Read/Write flag in slave mode
: Data / Address flag in slave mode
: Stop flag in slave & master mode
: Start flag in slave & master mode
: Busy flag in slave & master mode
I2CACK
2
2
C Status Register
R (0)
C Master Interrupt Flag in slave & master mode.
I2CRW
MiDAS1.0B Family
R (0)
I2CDA
R (0)
[1] : Interrupt occurred.
[1] : Overflow occurred.
[1] : Read state
I2CP
R (0)
R (0)
I2CS
I2CBF
R (0)
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