gc80c521a CORERIVER Semiconductor, gc80c521a Datasheet - Page 62

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gc80c521a

Manufacturer Part Number
gc80c521a
Description
Flash / Isp / Iap 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
6.12. I2C : Overview
Master-Receiver Sequence
Master-Transmitter Sequence
Combined Format
S SLA
S SLA
The condition is identical to a start condition
The condition must occurs after a data transfer acknowledge pulse.
When Master does not want to release the bus, a repeated start condition must be generated without a stop condition.
A
/A
S
Sr
P
SLA
: Acknowledge
: Start
: Stop
: Repeated Start
: Nor Acknowledge
: Slave Address
R/W
R/W
(0)
(1)
[7-bit Address Mode]
[7-bit Address Mode]
A
A
Dat
Dat
a
a
A
A
Data
Data /A P
/A
A
P
S SLA1
S SLA1
R/W
R/W
(0)
(0)
Sr SLA1
[10-bit / Extended 15-bit Address Mode]
[10-bit / Extended 15-bit Address Mode]
A
A
From Master to Slave
SLA2
SLA2
R/W
(1)
A
A
A
Data
Data
MiDAS1.0B Family
A
A
From Slave to Master
Data
Data /A P
/A
A
P
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