mpc5125 Freescale Semiconductor, Inc, mpc5125 Datasheet - Page 75
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mpc5125
Manufacturer Part Number
mpc5125
Description
Mpc5125 Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC5125.pdf
(92 pages)
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4.3.15.3
NOTES:
1
Freescale Semiconductor
(CLKPOL=0)
(SyncPol= 1)
FrameSync
Output timing is specified at a nominal 50 pF load.
Sym
Sdata_out
10
11
1
2
3
4
5
6
7
8
9
Sdata_in
Output
Output
BitClk
Input
Input
SCK cycle time, programable in the PSC CCS register
SCK pulse width, 50% SCK duty cycle
Slave select clock delay, programable in the PSC CCS register
Output data valid after slave select (SS)
Output data valid after SCK
Input data setup time
Input data hold time
Slave disable lag time
Sequential transfer delay, programable in the PSC CTUR / CTLR register
Clock falling time
Clock rising time
SPI Mode
Table 42. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
4
5
6
1
Figure 40. Timing Diagram — AC97 Mode
MPC5125 Microcontroller Data Sheet, Rev. 3
3
7
Description
2
Electrical and Thermal Characteristics
30.0
15.0
30.0
15.0
Min
6.0
1.0
—
—
—
—
—
TSCK
Max
8.9
8.9
7.9
7.9
—
—
—
—
—
—
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SpecID
A20.26
A20.27
A20.28
A20.29
A20.30
A20.31
A20.32
A20.33
A20.34
A20.35
A20.36
75