mpc5125 Freescale Semiconductor, Inc, mpc5125 Datasheet - Page 34

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mpc5125

Manufacturer Part Number
mpc5125
Description
Mpc5125 Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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NOTES:
1
2
3
4
5
l
Pins controlled by the STD_PU_ST register have a Schmitt trigger input; pins controlled by the STD_PU register do not. Pins controlled by the
IO_CONTROL_MEM register access their alternate function ALT3 by setting the IO_CONTROL_MEM[16BIT] bit. This setting applies to all pins controlled by
IO_CONTROL_MEM. Pins not controlled by these registers are indicated with a “—”.
Offset from IOCONTROL_BASE (default is 0xFF40_A000).
Except where noted in the Notes column, ALT0 is the primary (default) function for each pin after reset.
Alternate functions are chosen by setting the values of the STD_PU[FUNCMUX] bitfields inside the I/O Control module.
– STD_PU[FUNCMUX] = 00 → ALT0 (default)
– STD_PU[FUNCMUX] = 01 → ALT1
– STD_PU[FUNCMUX] = 10 → ALT2
– STD_PU[FUNCMUX] = 11→ ALT3
For selecting alternate functions, the STD_PU and STD_PU_ST registers function the same. When no function is available on a pin’s given ALTn function (value
of STD_PU[FUNCMUX] ), it is shown as “—”.
Module included on the MCU.
TEST
Pin
and Offset
Register
Control
Pad I/O
1
2
ALT0
ALT1
ALT2
ALT3
Function
Alternate
3
TEST
Table 2. MPC5125 Pin Multiplexing (continued)
Functions
4
Test/Debug
Peripheral
5
Direction
I/O
I
Power Domain
VDD_IO
2. This pin is an input only.
This pin cannot be configured.
4. This test pin must be tied to
VSS.
Notes
D14
Pin

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