mpc5125 Freescale Semiconductor, Inc, mpc5125 Datasheet - Page 71

• Manufacturer Part Number: mpc5125
• Description: Mpc5125 Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

4.3.12
The CAN functions are available as TX pins at normal IO pads and as RX pins at the VBAT domain. There is no filter for the
wakeup dominant pulse. Any high-to-low edge can cause wakeup, if configured.
4.3.13
This section specifies the timing parameters of the inter-integrated circuit (I
NOTES:
1
NOTES:
1
2
3
4
Freescale Semiconductor
Inter-peripheral clock is defined in the MPC5125 Reference Manual (MPC5125RM)
Output timing is specified at a nominal 50 pF load.
Programming IFDR with the maximum frequency results in the minimum output timings listed. The I
scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and
division values programmed in IFDR.
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time that SCL or SDA
takes to reach a high level depends on external signal capacitance and pullup resistor values.
Inter -peripheral Clock is defined in the MPC5125 Reference Manual (MPC5125RM).
Sym
Sym
1
2
3
4
5
6
7
8
9
1
2
4
6
7
8
9
4
2
2
2
2
2
2
2
2
Start condition hold time
Clock low time
Data hold time
Clock high time
Data setup time
Start condition setup time ( for repeated start condition only )
Stop condition setup time
Start condition hold time
Clock low time
SCL / SDA rise time
Data hold time
SCL / SDA fall time
Clock high time
Data setup time
Start condition setup time ( for repeated start condition only )
Stop condition setup time
CAN
I
2
C
Table 38. I
Table 37. I
Description
Description
2
MPC5125 Microcontroller Data Sheet, Rev. 3
C Output Timing Specifications — SCL and SDA
2
C Input Timing Specifications — SCL and SDA
2
C) interface. Refer to the I
Min
10
10
20
10
—
—
Min
0.0
0.0
6
7
2
2
8
4
2
2
Electrical and Thermal Characteristics
Max
Max
7.9
7.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
2
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
C interface is designed to
2
Units
C bus specification.
Units
ns
ns
ns
ns
3
3
3
3
3
3
3
1
1
1
1
1
SpecID
SpecID
A18.10
A18.11
A18.12
A18.13
A18.14
A18.15
A18.16
A18.1
A18.2
A18.3
A18.4
A18.5
A18.6
A18.7
A18.8
A18.9
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