mpc89l515ap Megawin Technology, mpc89l515ap Datasheet - Page 11

• Manufacturer Part Number: mpc89l515ap
• Description: 8-bit Micro-controller
• Manufacturer: Megawin Technology

FZWDTCR: Used to freeze the WDT-controlling register.
OSCDN: Used to adjust the behavior of crystal oscillator.
HWBS: Used to configure the MPC89x515A boot from ISP program or normal application program after the
EN6T: Used to configure the MPC89x515A run in 6T 12T mode or 6T mode.
The default value of the OR1 is FFh.
NVM register: OR1 (Option Register 1):
RAM
There are 1280 bytes RAM built in MPC89x515A.
The user can visit the leading 128-byte RAM via direct addressing instructions, we have named
those RAM as direct RAM that occupies address space 00h to 7Fh.
Followed 128-byte RAM can be visited via indirect addressing instructions, we have named those
RAM as indirect RAM that occupied address space 80h to FFh.
The other 1024-byte RAM is named expanded RAM that still occupied address space 0000h to
03FFh. An user can access it via general register Ri, or via data pointers DPTR associated with
MOVX instructions, say
instruction MOVX which is designed to access external memory, the user can set the bit ERAM in
SFR AUXR as 1, and by doing so is to hide the expanded RAM and to visit the external memory.
FZWDTCR
MEGAWIN
Bit-7
0:= The MPC89x515A will run in 6T mode
1:= The MPC89x515A will run in 12T mode
0:= The MPC89x515A will boot from ISP start address after power-on.
1:= No operation. The MPC89x515A will boot from normal application program.
power-on sequence.
1:= The gained of crystal oscillator is enough for oscillator to start oscillating up to 48MHz.
0:= The DC gained of crystal oscillator amplifier is doubled but bandwidth is reduced. It will bring
1:= (default) Permit all the reset events from power-up, software and the Watch Dog Timer
0 := Configure the SFR WDTCR to be reset only via power-up action, not by software reset nor
help to EMI reducing and improve the power consumption. Dealing with application does
not need high frequency clock (under 20MHz). It is recommended to do so.
could reset the SFR WDTCR.
Bit-6
reset from the Watch Dog Timer.
MOVX
Bit-5
A, @R1
MPC89x515A Data Sheet
OSCDN
Bit-4
or
MOVX
Bit-3
A, @DPTR
Bit-2
. To reserve the natural characteristic of
HWBS
Bit-1
EN6T
Bit-0
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