mpc8379e Freescale Semiconductor, Inc, mpc8379e Datasheet - Page 4

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mpc8379e

Manufacturer Part Number
mpc8379e
Description
Powerquicc Ii Pro Processor Hardware Specifications
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Overview
1.3
The eTSECs include the following features:
1.4
The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a
flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with
the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.
Interrupts can also be redirected to an external interrupt controller.
1.5
The power management controller includes the following features:
1.6
The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
1.7
The device provides an integrated four-channel DMA controller with the following features:
4
Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI
Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,
IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588™ standards
Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
MII management interface for external PHY control and status
Provides power management when the device is used in both host and agent modes
Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states
Support for PME generation in PCI agent mode, PME detection in PCI host mode
Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)
Supports MPC8349E backward-compatibility mode
Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters)
Supports misaligned transfers
Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
Integrated Programmable Interrupt Controller (IPIC)
Power Management Controller (PMC)
Serial Peripheral Interface (SPI)
DMA Controller, Dual I
(eLBC), and Timers
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
2
C, DUART, Enhanced Local Bus Controller
Freescale Semiconductor

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