mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 83

• Manufacturer Part Number: mpc8349ea
• Description: Mpc8349ea Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Revision
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MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
12/2006
11/2006
2/2007
1/2007
8/2006
4/2006
3/2006
Date
Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified T
Page 1, updated first paragraph to reflect PowerQUICC II Pro information.
In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to t
deleted original note 3; renumbered the remaining notes.
In Figure 41, “JTAG Interface Connection,” updated with new figure.
In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced third sentence of first
paragraph directing customer to product summary page for available frequency configuration parts.
Updated back page information.
In Table 1, “Absolute Maximum Ratings,” added “(1.36 max for 667-MHz core frequency)” to max V
and Av
In Table 2, “Recommended Operating Conditions,” added a row showing nominal core supply voltage
and PLL supply voltage of 1.3 V for 667-MHz parts.
In Table 4, “MPC8349EA Power Dissipation,” added two footnotes to 667-MHz row showing nominal
core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts.
In Table 54, “MPC8349EA (TBGA) Pinout Listing,” updated V
supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts.
from 900 ps to 775 ps.
Updated note in introduction.
In the features list in Section 1, “Overview,” corrected DDR data rate to show:
In Section 23, “Ordering Information,” replicated note from document introduction.
Changed all references to revision 2.0 silicon to revision 3.0 silicon.
Changed VIH minimum value in Table 40, “JTAG Interface DC Electrical Characteristics,” to
OV
In Table 66, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.
In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min = 2
and max = OV
Updated DDR2 I/O power values in
Removed Table 20, “Timing Parameters for DDR2-400.”
Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC Timing
Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
Changed Min and Max values for V
In Table 55, “MPC8349EA (TBGA) Pinout Listing,” modified rows for MDICO and MDIC1 signals and
added note “It is recommended that MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied
to DDR power using an 18 Ω resistor.”
In Table 55, “MPC8349EA (TBGA) Pinout Listing,” in row AVDD3 changed power supply from
“AVDD3” to “—.”
Initial release.
• 400 MHz for DDR2 for TBGA parts for silicon 3.x
DD
– 0.3.
DD
Table 65. Document Revision History (continued)
values.
DD
+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
IH
Table
and V
Substantive Change(s)
5, “MPC8349EA Typical I/O Power Dissipation.”
IL
in Table 44,“PCI DC Electrical Characteristics.”
DD
and AV
DD
rows to show nominal core
Document Revision History
ddkhds
for 333 MHz
CISKEW
and
DD
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