mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 81

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mpc8349ea

Manufacturer Part Number
mpc8349ea
Description
Mpc8349ea Powerquicc
Manufacturer
Freescale Semiconductor, Inc
Datasheet
V
drive current is then I
Table 64
nominal OV
21.6
The MPC8349EA power-on configuration options can be set through external pull-up or pull-down
resistors of 4.7 kΩ on certain output pins (see the customer-visible configuration pins). These pins are used
as output only pins in normal operation.
However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched
when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal
function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with
the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed
for the output pins.
21.7
The MPC8349EA requires high resistance pull-up resistors (10 kΩ is recommended) on open-drain pins,
including I
For more information on required pull-up resistors and the connections required for the JTAG interface,
refer to application note AN2931, PowerQUICC™ Design Checklist.
Freescale Semiconductor
Note: Nominal supply voltages. See
2
Impedance
Differential
= (1/(1/R
R
R
N
P
summarizes the signal impedance targets. The driver impedance are targeted at minimum V
Pull-Up Resistor Requirements
Configuration Pin Multiplexing
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
2
C pins, the Ethernet Management MDIO pin, and IPIC interrupt pins.
DD
1
+ 1/R
, 105°C.
Configuration, Power
Local Bus, Ethernet,
DUART, Control,
2
Management
)) × I
source
42 Target
42 Target
NA
source
= V
. Solving for the output impedance gives R
Table
1
/R
source
Table 64. Impedance Characteristics
1, T
(Not Including PCI
j
.
= 105°C.
Output Clocks)
PCI Signals
25 Target
25 Target
NA
PCI Output Clocks
PCI_SYNC_OUT)
(Including
42 Target
42 Target
NA
source
DDR DRAM
20 Target
20 Target
= R
NA
term
System Design Information
× (V
Symbol
Z
1
DIFF
Z
Z
/V
0
0
2
– 1). The
Unit
W
W
W
DD
81
,

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