mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 68

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mpc8349ea

Manufacturer Part Number
mpc8349ea
Description
Mpc8349ea Powerquicc
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clocking
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
and
CLKIN/PCI_SYNC_IN ratios.
68
Table 59
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
CFG_CLKIN_DIV
show the expected frequency values for the CSB frequency for select csb_clk to
at Reset
Section 19, “Clocking,”
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
1
Table 57. System PLL Multiplication Factors (continued)
Table 58. CSB Frequency Options for Host Mode
SPMF
RCWL[SPMF]
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1010
1011
1100
1101
1110
1111
the LBIUCM, DDRCM, and SPMF parameters in the reset
Input Clock
csb_clk :
Ratio
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
16 : 1
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
7 : 1
8 : 1
9 : 1
System PLL Multiplication
2
100
116
133
150
166
183
200
216
Factor
16.67
233
250
266
× 10
× 11
× 12
× 13
× 14
× 15
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
100
125
150
175
200
225
250
275
300
325
25
33.33
100
133
166
200
233
266
300
333
Freescale Semiconductor
66.67
2
133
200
266
333
Table 58

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