mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 65

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mpc8349ea

Manufacturer Part Number
mpc8349ea
Description
Mpc8349ea Powerquicc
Manufacturer
Freescale Semiconductor, Inc
Datasheet
19 Clocking
Figure 40
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8349EA is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8349EA to function. When the
MPC8349EA is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN
signal should be tied to GND.
Freescale Semiconductor
CFG_CLKIN_DIV
shows the internal distribution of the clocks.
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
CLKIN
System PLL
Figure 40. MPC8349EA Clock Subsystem
e300 Core
PCI Clock
csb_clk
Clock
Divider
Unit
csb_clk to Rest
of the Device
ddr_clk
lbiu_clk
Core PLL
To Local Bus
Controller
Memory
Controller
To DDR
Memory
Clock
DDR
LBIU
/n
DLL
Div
/2
core_clk
6
6
8
MCK[0:5]
LCLK[0:2]
LSYNC_OUT
LSYNC_IN
MCK[0:5]
PCI_SYNC_OUT
PCI_CLK_OUT[0:7]
PCI_CLK/
PCI_SYNC_IN
DDR
Memory
Device
Local Bus
Memory
Device
Clocking
65

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