mc68hc08az60 Freescale Semiconductor, Inc, mc68hc08az60 Datasheet - Page 253

• Manufacturer Part Number: mc68hc08az60
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

PWM Initialization
11-timb
MOTOROLA
NOTE:
NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H–TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
1. In the TIMB status and control register (TBSC):
2. In the TIMB counter modulo registers (TBMODH–TBMODL), write
3. In the TIMB channel x registers (TBCHxH–TBCHxL), write the
4. In TIMB channel x status and control register (TBSCx):
5. In the TIMB status control register (TBSC), clear the TIMB stop bit,
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a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter by setting the TIMB reset bit, TRST.
the value for the required PWM period.
value for the required pulse width.
a. Write 0:1 (for unbuffered output compare or PWM signals) or
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
TSTOP.
Timer Interface Module B (TIMB)
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB–MSxA. (See
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See
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Table
Timer Interface Module B (TIMB)
MC68HC08AZ60 — Rev 1.0
2).
Functional Description
Table
2.)
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