mc68hc908mr8 Freescale Semiconductor, Inc, mc68hc908mr8 Datasheet - Page 262

no-image

mc68hc908mr8

Manufacturer Part Number
mc68hc908mr8
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc68hc908mr8CFA
Manufacturer:
FREESCALE
Quantity:
1 831
Part Number:
mc68hc908mr8CFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68hc908mr8CP
Manufacturer:
FREESCALE
Quantity:
3
Serial Communications Interface (SCI)
13.5 Wait Mode
13.6 Stop Mode
13.7 SCI During Break Module Interrupts
Technical Data
262
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
The SCI module remains active after the execution of a WAIT
instruction. In wait mode the SCI module registers are not accessible by
the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
The SCI module is inactive after execution of a STOP instruction. The
STOP instruction does not affect register conditions of the SCI. SCI
operation resumes when the MCU exits stop mode after an external
interrupt.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during interrupts generated by the break
module. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
Serial Communications Interface (SCI)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor

Related parts for mc68hc908mr8