mc68hc908mr8 Freescale Semiconductor, Inc, mc68hc908mr8 Datasheet - Page 102

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mc68hc908mr8

Manufacturer Part Number
mc68hc908mr8
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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System Integration Module (SIM)
7.6.1.1 Hardware Interrupts
Technical Data
102
INTERRUPT
I BIT
R/W
IDB
IAB
MODULE
NOTE:
SP – 4
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first.
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
CCR
Figure 7-10. Interrupt Recovery
SP – 3
System Integration Module (SIM)
A
SP – 2
X
SP – 1
PC – 1[7:0] PC – 1[15:8] OPCODE
SP
PC
PC + 1
OPERAND
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Figure 7-11

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