mc68hc908mr8 Freescale Semiconductor, Inc, mc68hc908mr8 Datasheet - Page 117

• Manufacturer Part Number: mc68hc908mr8
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f
frequency, f
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency, f
The VCO’s output clock, CGMVCLK, running at a frequency f
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency, f
8.4.2.4 Programming the PLL
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the dc voltage on the external capacitor connected to
CGMXFC based on the width and direction of the correction pulse. The
filter can make fast or slow corrections depending on its mode,
described in
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f
condition based on this comparison.
Clock Generator Module (CGM)
RDV
NOM
8.4.2.2 Acquisition and Tracking
. The circuit determines the mode of the PLL and the lock
, (4.9152 MHz) times a linear factor L, or (L) f
RDV
= f
RCLK
.
VRS
for more information.
is equal to the nominal center-of-range
RCLK
, and is fed to the PLL through a
Clock Generator Module (CGM)
Modes. The value of the
VDV
Functional Description
= f
VCLK/N
Technical Data
VCLK
NOM
VRS
, is fed
. See
.
.
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