mc68hc908mr8 Freescale Semiconductor, Inc, mc68hc908mr8 Datasheet - Page 232

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mc68hc908mr8

Manufacturer Part Number
mc68hc908mr8
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Timer Interface B (TIMB)
12.4.4.1 Unbuffered PWM Signal Generation
Technical Data
232
The value in the TIMB counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMB counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see
The value in the TIMB channel registers determines the pulse width of
the PWM output. The pulse width of an 8-bit PWM signal is variable in
256 increments. Writing $0080 (128) to the TIMB channel registers
produces a duty cycle of 128/256 or 50 percent.
Any output compare channel can generate unbuffered PWM pulses as
described in
unbuffered because changing the pulse width requires writing the new
pulse width value over the value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change a
pulse width value could cause incorrect operation for up to two PWM
periods. For example, writing a new value before the counter reaches
the old value but after the counter reaches the new value prevents any
compare during that PWM period. Also, using a TIMB overflow interrupt
routine to write a new, smaller pulse width value may cause the compare
to be missed. The TIMB may pass the new value before it is written to
the TIMB channel registers.
PTBx/TCHx
OVERFLOW
12.4.4 Pulse-Width Modulation
Figure 12-3. PWM Period and Pulse Width
Timer Interface B (TIMB)
PULSE
WIDTH
12.10.1 TIMB Status and Control
PERIOD
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
(PWM). The pulses are
MC68HC908MR8 — Rev 4.1
OVERFLOW
Freescale Semiconductor
Register).
COMPARE
OUTPUT

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