mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 83

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

7.5.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the programming information for the high byte of
the modulo feedback divider.
MUL11–MUL8 — Multiplier Select Bits
PMSH[7:4] — Unimplemented Bits
7.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
MUL7–MUL0 — Multiplier Select Bits
Freescale Semiconductor
These read/write bits control the high byte of the modulo feedback divider that selects the VCO
frequency multiplier N. (See
the multiplier select registers configures the modulo feedback divider the same as a value of $0001.
Reset initializes the registers to $0040 for a default multiply value of 64.
These bits have no function and always read as logic 0s.
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
Address:
Address:
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 7-6. PLL Multiplier Select Register High (PMSH)
$0038
$0038
Figure 7-7. PLL Multiplier Select Register Low (PMSL)
MUL7
Bit 7
Bit 7
0
0
0
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
= Unimplemented
7.3.3 PLL Circuits
7.3.3 PLL Circuits
MUL6
6
0
0
6
1
MUL5
5
0
0
5
0
NOTE
NOTE
and
and
MUL4
4
0
0
4
0
7.3.6 Programming the
7.3.6 Programming the
MUL11
MUL3
3
0
3
0
MUL10
MUL2
2
0
2
0
MUL9
MUL1
PLL.) MUL7–MUL0 cannot
PLL.) A value of $0000 in
1
0
1
0
MUL8
MUL0
Bit 0
Bit 0
0
0
CGMC Registers
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