ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 99

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Energy Registers
AVAHR
BVAHR
CVAHR
Note: In 3-phase three wire case (CONSEL[1:0]=01), the ADE7880 computes the rms value of the line voltage between phases A and C
and stores the result into BVRMS register (see Voltage RMS in 3-phase three wire delta configurations for more details). Consequently,
the ADE7880 computes powers associated with phase B that do not have physical meaning. To avoid any errors in the frequency output
pins CF1, CF2 or CF3 related to these powers, disable the contribution of phase B to the energy to frequency converters by setting bits
TERMSEL1[1] or TERMSEL2[1] or TERMSEL3[1] to 0 in COMPMODE register (See Energy-to-Frequency Conversion for more
details).
Table 48. LCYCMODE Register (Address 0xE702)
Bit
Location
0
1
2
3
4
5
6
7
Table 49. HSDC_CFG Register (Address 0xE706)
Bit
Location
0
1
Bit Mnemonic
LWATT
LVAR
LVA
ZXSEL[0]
ZXSEL[1]
ZXSEL[2]
RSTREAD
PFMODE
Bit Mnemonic
HCLK
HSIZE
Default Value
0
0
0
1
1
1
1
0
Default Value
0
0
CONSEL[1:0] = 00
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms
Description
0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed in regular accumulation mode.
1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed into line cycle accumulation mode.
0: the var-hour accumulation registers (AFVARHR, BFVARHR, and CFVARHR) are placed in
regular accumulation mode.
1: the var-hour accumulation registers (AFVARHR, BFVARHR, and CFVARHR) are placed into
line-cycle accumulation mode.
0: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed in regular
accumulation mode.
1: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed into line-cycle
accumulation mode.
0: Phase A is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase A is selected for zero-crossings counts in the line cycle accumulation mode. If more
than one phase is selected for zero-crossing detection, the accumulation time is shortened
accordingly.
0: Phase B is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase B is selected for zero-crossings counts in the line cycle accumulation mode.
0: Phase C is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase C is selected for zero-crossings counts in the line cycle accumulation mode.
0: read-with-reset of all energy registers is disabled. Clear this bit to 0 when Bits[2:0] (LWATT,
LVAR, and LVA) are set to 1.
1: enables read-with-reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR
registers. This means a read of those registers resets them to 0.
0: power factor calculation uses instantaneous values of various phase powers used in its
expression
1: power factor calculation uses phase energies values calculated using line cycle
accumulation mode. Bits LWATT and LVA in LCYCMODE register must be enabled for the
power factors to be computed correctly. The update rate of the power factor measurement
in this case is the integral number of half line cycles that are programmed into the LINECYC
register.
Description
0: HSCLK is 8 MHz.
1: HSCLK is 4 MHz.
0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.
1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.
CONSEL[1:0] = 01
VA rms × IA rms
VB rms × IB rms
VB = VA – VC (See Note)
VC rms × IC rms
Rev. PrE| Page 99 of 103
CONSEL[1:0] = 10
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms
CONSEL[1:0] = 11
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms
ADE7880