ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 51

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Similar to active and reactive powers, the ADE7880 achieves the
integration of the apparent power signal in two stages (see Figure
54). The first stage accumulates the instantaneous apparent
power at 1.024MHz, although they are computed by the DSP at
8KHz rate. Every time a threshold is reached, a pulse is
generated and the threshold is subtracted from the internal
register. The second stage consists in accumulating the pulses
generated after the first stage into internal 32-bit accumulation
registers. The content of these registers is transferred to the VA-
hour registers, xVAHR, when these registers are accessed.
Figure 54 illustrates this process. The threshold is formed by the
VATHR 8-bit unsigned register concatenated to 27 bits equal to
0. It is introduced by the user and is common for all phase total
active and fundamental powers. Its value depends on how much
energy is assigned to one LSB of VA-hour registers. When a
derivative of apparent energy (VAh) [10
integer, is desired as one LSB of the xVAHR register, the
xVATHR register can be computed using the following equation:
where:
PMAX =27,059,678=0x19CE5DE, the instantaneous power
computed when the ADC inputs are at full scale.
f
power computed by the DSP at 8KHz is accumulated.
U
the ADC inputs are at full scale.
VATHR register is an 8-bit unsigned number, so its maximum
value is 2
is 2 or 1 should be avoided and 0 should never be used as the
threshold must be a non-zero value.
This discrete time accumulation or summation is equivalent to
integration in continuous time following the description in
Equation 44.
where:
n is the discrete time sample number.
T is the sample period.
In the ADE7880, the phase apparent powers are accumulated in
the AVAHR, BVAHR, and CVAHR 32-bit signed registers. The
apparent energy register content can roll over to full-scale
negative (0x80000000) and continue increasing in value when the
apparent power is positive. Conversely, if because of offset
compensation in the rms datapath, the apparent power is negative,
the energy register underflows to full-scale positive
(0x7FFFFFFF) and continues to decrease in value.
S
FS
= 1.024MHz, the frequency at which every instantaneous
, I
VATHR
FS
ApparentEn
are the rms values of phase voltages and currents when
8
– 1. Its default value is 0x3. Values lower than 3, that
=
PMAX
ergy
U
=
FS
×
∫
s
×
f
( )
s
t
I
×
FS
dt
3600
×
=
2
Lim
27
T
×
→
0
10



n
n
n
∑
∞
VAh], where n is an
=
0
s
( )
nT
×
T



Rev. PrE | Page 51 of 103
(43)
(44)
The ADE7880 provides a status flag to signal when one of the
xVAHR registers is half full. Bit 4 (VAEHF) in the STATUS0
register is set when Bit 30 of one of the xVAHR registers
changes, signifying one of these registers is half full. As the
apparent power is always positive and the xVAHR registers are
signed, the VA-hour registers become half full when they
increment from 0x3FFFFFFF to 0x4000 0000. Interrupts
attached to Bit VAEHF in the STATUS0 register can be enabled by
setting Bit 4 in the MASK0 register. If enabled, the IRQ0 pin is set
low and the status bit is set to 1 whenever one of the Energy
Registers xVAHR becomes half full. The status bit is cleared and
the
to the STATUS0 register with the corresponding bit set to 1.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
read-with-reset for all xVAHR accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period for the accumulation register is
976.5625ns (1.024 MHz frequency). With full-scale pure
sinusoidal signals on the analog inputs, the average word value
representing the apparent power is PMAX. If the VATHR
threshold register is set at 3, its minimum recommended value,
the first stage accumulator generates a pulse that is added to the
xVAHR registers every
The maximum value that can be stored in the xVAHR
accumulation register before it overflows is 2
0x7FFFFFFF. The integration time is calculated as
Energy Accumulation Mode
The apparent power accumulated in each accumulation register
depends on the configuration of Bits[5:4] (CONSEL[1:0]) in the
ACCMODE register. The various configurations are described
in Table 19.
Table 19. Inputs to VA-Hour Accumulation Registers
CONSEL[1:0]
00
01
10
11
Note: In 3-phase three wire case (CONSEL[1:0]=01), the
ADE7880 computes the rms value of the line voltage between
phases A and C and stores the result into BVRMS register (see
Voltage RMS in 3-phase three wire delta configurations for
more details). Consequently, the ADE7880 computes powers
IRQ0 pin is set to high by writing
Time = 0x7FFF,FFFF × 14.531 μs = 8 hr 40 min 6 sec (45)
AVAHR
AVRMS × AIRMS
AVRMS × AIRMS
AVRMS × AIRMS
AVRMS × AIRMS
PMAX
3
×
×
BVAHR
BVRMS × BIRMS
BVRMS × BIRMS
VB = VA − VC
(See Note)
BVRMS × BIRMS
VB = −VA − VC
BVRMS × BIRMS
VB = −VA
. 1
2
024
27
×
10
6
31
=
− 1 or
14
.
CVAHR
CVRMS × CIRMS
CVRMS × CIRMS
CVRMS × CIRMS
CVRMS × CIRMS
ADE7880
531
µ
sec
.