ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 26

no-image

ade7880

Manufacturer Part Number
ade7880
Description
Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
Manufacturer
Analog Devices, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ade7880ACPZ
Manufacturer:
ADI
Quantity:
5
Part Number:
ade7880ACPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ade7880ACPZ-RL
Manufacturer:
AD
Quantity:
2 155
Part Number:
ade7880ACPZ-RL
Manufacturer:
AD
Quantity:
12 620
Part Number:
ade7880ACPZ-RL
Manufacturer:
AD
Quantity:
2 550
Part Number:
ade7880ACPZ-RL
Manufacturer:
AD
Quantity:
7 700
Part Number:
ade7880ACPZ-RL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADE7880
offset on the current channel. All filters are implemented in the
DSP and, by default, they are all enabled: the bit 0 (HPFEN) of
CONFIG3[7:0] register is set to 1. All filters are disabled by
setting bit 0 (HPFEN) to 0.
Current Channel Sampling
The waveform samples of the current channel are taken at the
output of HPF and stored in the 24-bit signed registers, IAWV,
IBWV, ICWV, and INWV at a rate of 8 kSPS. All power and rms
calculations remain uninterrupted during this process. Bit 17
(DREADY) in the STATUS0 register is set when the IAWV,
IBWV, ICWV, and INWV registers are available to be read using
the I
MASK0 register enables an interrupt to be set when the
DREADY flag is set. See the Digital Signal Processor section for
more details on Bit DREADY.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
When the IAWV, IBWV, ICWV, and INWV 24-bit signed
registers are read from the ADE7880, they are transmitted sign
extended to 32 bits. See Figure 19 for details.
The ADE7880 contains a high speed data capture (HSDC) port
that is specially designed to provide fast access to the waveform
sample registers. See the HSDC Interface section for more details.
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
The di/dt sensor detects changes in the magnetic field caused by
the ac current. Figure 20 shows the principle of a di/dt current
sensor.
The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. The
changes in the magnetic flux density passing through a conductor
loop generate an electromotive force (EMF) between the two
ends of the loop. The EMF is a voltage signal that is propor-
tional to the di/dt of the current. The voltage output from the
di/dt current sensor is determined by the mutual inductance
between the current carrying conductor and the di/dt sensor.
2
Figure 19. 24-Bit IxWV Register Transmitted as 32-Bit Signed Word
C or SPI serial port. Setting Bit 17 (DREADY) in the
31
EQUAL TO BIT 23
BITS[31:24] ARE
Figure 20. Principle of a di/dt Current Sensor
24 23 22
MAGNETIC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
BIT 23 IS A SIGN BIT
24-BIT SIGNED NUMBER
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
0
Rev. PrE | Page 26 of 103
Due to the di/dt sensor, the current signal needs to be filtered
before it can be used for power measurement. On each phase and
neutral current datapath, there are built-in digital integrators to
recover the current signal from the di/dt sensor. The digital
integrators placed on the phase currents data paths are independent
of the digital integrator placed in the neutral current data path. This
allows for using a different current sensor to measure the neutral
current (for example a current transformer) from the current
sensors used to measure the phase currents (for example di/dt
sensors). The digital integrators are managed by Bit 0 (INTEN) of
the CONFIG register and by Bit 3 (ININTEN) of the CONFIG3
register. Bit 0 (INTEN) of the CONFIG register manages the
integrators in the phase current channels. Bit 3 (ININTEN) of the
CONFIG3 register manages the integrator in the neutral current
channel. When INTEN bit is 0 (default), all integrators in the phase
current channels are disabled. When INTEN bit is 1, the integrators
in the phase currents datapaths are enabled. When ININTEN bit is
0 (default), the integrator in the neutral current channel is disabled.
When ININTEN bit is 1, the integrator in the neutral current
channel is enabled.
Figure 21 and Figure 22 show the magnitude and phase
response of the digital integrator.
Note that the integrator has a −20 dB/dec attenuation and
approximately −90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. However, the di/dt
sensor has a 20 dB/dec gain associated with it and generates sig-
nificant high frequency noise. At least a second order
antialiasing filter is needed to avoid noise aliasing back in the
band of interest when the ADC is sampling (see the
Antialiasing Filter section).
The DICOEFF 24-bit signed register is used in the digital
integrator algorithm. At power-up or after a reset, its value is
0x000000. Before turning on the integrator, this register must be
–100
–50
–50
50
0
0
0.01
Figure 21. Combined Gain and Phase Response of the
0
500
0.1
Preliminary Technical Data
1000
Digital Integrator
1500
1
FREQUENCY (Hz)
FREQUENCY (Hz)
2000
10
2500
100
3000
3500
1000
4000

Related parts for ade7880