ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 67

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
state of all phases relative to a no load condition and are set
simultaneously with Bit FNLOAD in the STATUS1 register.
FNLPHASE[0] indicates the state of Phase A, FNLPHASE[1]
indicates the state of Phase B, and FNLPHASE[2] indicates the
state of Phase C. When Bit FNLPHASE[x] is cleared to 0, it
means the phase is out of the no load condition. When set to 1,
it means the phase is in a no load condition.
An interrupt attached to the Bit 1 (FNLOAD) in the STATUS1
register can be enabled by setting Bit 1 in the MASK1 register. If
enabled, the IRQ1 pin is set low and the status bit is set to 1
whenever one of three phases enters or exits this no load
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Then the status bit is cleared and the
pin is set back high by writing to the STATUS1 register with the
corresponding bit set to 1.
No Load Detection Based on Apparent Power
This no load condition is triggered when no less significant bits
are accumulated into the apparent energy register on one phase
(xVAHR, x=A, B or C) for a time indicated by the APNOLOAD
unsigned 16-bit register. In this case, the apparent energy of that
phase is not accumulated and no CFx pulses are generated
based on this energy.
The expression used to compute the VANOLOAD unsigned 16-
bit value is
where:
Y is the required no load current threshold computed relative to
full scale. For example, if the no load threshold current is set
10,000 times lower than full scale value, then Y=10,000.
VATHR is the VATHR register used as the threshold of the first
stage energy accumulator (see Apparent Energy Calculation
section)
PMAX=27,059,678=0x19CE5DE, the instantaneous apparent
power computed when the ADC inputs are at full scale.
detection circuit is disabled.
Bit 2 (VANLOAD) in the STATUS1 register is set when this no
load condition in one of the three phases is triggered. Bits[8:6]
(VANLPHASE[2:0]) in the PHNOLOAD register indicate the
state of all phases relative to a no load condition and they are set
simultaneously with Bit VANLOAD in the STATUS1 register:
•
•
•
When the VANOLOAD register is set to 0x0, the no load
Bit VANLPHASE[0] indicates the state of Phase A.
Bit VANLPHASE[1] indicates the state of Phase B.
Bit VANLPHASE[2] indicates the state of Phase C.
VANOLOAD
=
2
16
−
Y
×
VATHR
PMAX
×
2
17
IRQ1
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When Bit VANLPHASE[x] is cleared to 0, it means the phase is
out of no load condition. When set to 1, it means the phase is in
no load condition.
An interrupt attached to Bit 2 (VANLOAD) in the STATUS1
register is enabled by setting Bit 2 in the MASK1 register. If
enabled, the IRQ1 pin is set low and the status bit is set to 1
whenever one of three phases enters or exits this no load
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Next, the status bit is cleared, and the
pin is set to high by writing to the STATUS1 register with the
corresponding bit set to 1.
CHECKSUM REGISTER
The ADE7880 has a checksum 32-bit register, CHECKSUM, that
ensures the configuration registers maintain their desired value
during Normal Power Mode PSM0.
The registers covered by this register are MASK0, MASK1,
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG,
all registers located in the DSP data memory RAM between
addresses 0x4380 and 0x43BE and another eight 8-bit reserved
internal registers that always have default values. The ADE7880
computes the cyclic redundancy check (CRC) based on the
IEEE802.3 standard. The registers are introduced one-by-one
into a linear feedback shift register (LFSR) based generator
starting with the least significant bit (as shown in Figure 71).
The 32-bit result is written in the CHECKSUM register. After
power-up or a hardware/software reset, the CRC is computed
on the default values of the registers giving a result equal to
0xAFFA63B9.
Figure 72 shows how the LFSR works. The MASK0, MASK1,
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, and HSDC_CFG
registers, the registers located between addresses 0x4380 and
43BE and the eight 8-bit reserved internal registers form the bits
[a
of the first register to enter LFSR; Bit a
bit of the last register to enter LFSR. The formulas that govern
LFSR are as follows:
b
the CRC. Bit b
significant.
g
polynomial defined by the IEEE802.3 standard as follows:
i
i
, i = 0, 1, 2, …, 31 are the coefficients of the generating
(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that form
2271
, a
G(x) = x
x
g
g
0
8
5
2270
+ x
= g
= g
,…, a
1
10
4
= g
+ x
= g
32
0
2
0
2
+ x
11
] used by LFSR. Bit a
is the least significant bit, and Bit b
= g
+ x + 1
= g
26
4
= g
+ x
12
= g
5
23
= g
16
+ x
= g
7
22
= 1
22
+ x
= g
16
26
+ x
0
= g
is the least significant bit
2271
12
31
+ x
is the most significant
= 1
11
+ x
10
ADE7880
31
+ x
is the most
8
+ x
IRQ1
7
(49)
(50)
+