ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 63

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
rounded to the nearest integer. If CFxDEN is set equal to 0, then
the ADE7880 considers it to be equal to 1.
The CFx pulse output stays low for 80 ms if the pulse period is
larger than 160 ms (6.25 Hz). If the pulse period is smaller than
160 ms and CFxDEN is an even number, the duty cycle of the
pulse output is exactly 50%. If the pulse period is smaller than
The CFx pulse output is active low and preferably connected to
an LED, as shown in Figure 63.
Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the CFMODE
register decide if the frequency converter output is generated at
the CF3, CF2, or CF1 pin. When Bit CFxDIS is set to 1 (the
default value), the CFx pin is disabled and the pin stays high.
When Bit CFxDIS is cleared to 0, the corresponding CFx pin
output generates an active low signal.
Bits[16:14] (CF3, CF2, CF1) in the Interrupt Mask Register
MASK0 manage the CF3, CF2, and CF1 related interrupts.
When the CFx bits are set, whenever a high-to-low transition at
the corresponding frequency converter output occurs, an
interrupt IRQ0
register is set to 1. The interrupt is available even if the CFx
output is not enabled by the CFxDIS bits in the CFMODE
register.
Digital Signal Processor
phase A active
phase B active
phase C active
Instantaneous
Instantaneous
Instantaneous
power
power
power
Figure 63. CFx Pin Recommended Connection
is triggered and a status bit in the STATUS0
CFx pin
TERMSELx bits in
COMPMODE
Σ
V
DD
VA
WATT
FWATT
FVAR
CFxSEL bits in
Figure 62. Energy-to-Frequency Conversion
CFMODE
Rev. PrE | Page 63 of 103
2
x
7
34
WTHR
THRESHOLD
160 ms and CFxDEN is an odd number, the duty cycle of the
pulse output is
Σ
Synchronizing Energy Registers with CFx Outputs
The ADE7880 contains a feature that allows synchronizing the
content of phase energy accumulation registers with the
generation of a CFx pulse. When a high-to-low transition at one
frequency converter output occurs, the content of all internal
phase energy registers that relate to the power being output at
CFx pin is latched into hour registers and then resets to 0. See
Table 23 for the list of registers that are latched based on the
CFxSEL[2:0] bits in the CFMODE register. All 3-phase registers
are latched independent of the TERMSELx bits of the
COMPMODE register. The process is shown in Figure 64 for
CF1SEL[2:0] = 010 (apparent powers contribute at the CF1 pin)
and CFCYC = 2.
The CFCYC 8-bit unsigned register contains the number of
high to low transitions at the frequency converter output between
two consecutive latches. Avoid writing a new value into the
CFCYC register during a high-to-low transition at any CFx pin.
Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the
CFMODE register enable this process when set to 1. When
PHASE A AND
27
CF1 PULSE
APPARENT
BASED ON
26
(1+1/CFxDEN) × 50%
PHASE B
POWERS
Accumulator
0
Figure 64. Synchronizing AVAHR and BVAHR with CF1
Internal
ENERGY REGISTERS
0
CVAHR LATCHED
AVAHR, BVAHR,
RESET
2
x
7
CFCYC = 2
REVPSUMx bit of
STATUS0[31:0]
Freq Divider
CFxDEN
ENERGY REGISTERS
CVAHR LATCHED
AVAHR, BVAHR,
ADE7880
RESET
CFx pulse
output