ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 61

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
default value of 000 means the registers are updated every
125µsec (8 KHz rate). Other update periods are: 250 µsec
(HRATE=001), 1msec (010), 16msec (011), 128msec (100),
512msec (101), 1.024 sec (110). If HRATE bits are 111, then the
harmonic calculations are disabled.
The ADE7880 provides two ways to manage the harmonic
computations. The first approach, enabled when bit 0 (HRCFG)
of HCONFIG register is cleared to its default value of 0, sets bits
19 (HREADY) in STATUS0 register to 1 after a certain period
of time and then every time the harmonic calculations are
updated at HRATE frequency. This allows an external
microcontroller to access the harmonic calculations only after
they have settled. The time period is determined by the state of
bits 4, 3 (HSTIME) in HCONFIG register. The default value of
01 sets the time to 750msec, the settling time of the harmonic
calculations. Other possible values are 500msec (HSTIME=00),
1sec (10) and 1250msec (11).
The second approach, enabled when bit 0 (HRCFG) of
HCONFIG register is set to 1, sets bit 19 (HREADY) in
STATUS0 register to 1 every time the harmonic calculations are
updated at the update frequency determined by HRATE bits
without waiting for the harmonic calculations to settle. This
allows an external microcontroller to access the harmonic
calculations immediately after they have been started. If the
corresponding mask bit in the MASK0 interrupt mask register
is enabled, the
cleared and the pin
STATUS0 register with the corresponding bit set to 1.
Additionally, the ADE7880 provides a periodical output signal
called HREADY at CF2/HREADY pin synchronous to the
moment the harmonic calculations are updated in the harmonic
registers. This functionality is chosen if bit 2 (CF2DIS) is set to
1 in CONFIG register. If CF2DIS is set to 0 (default value), the
CF2 energy to frequency converter output is provided at
CF2/HREADY pin. The default state of this signal is high. Every
time the harmonic registers are updated based on HRATE bits
in HCONFIG register, the signal HREADY goes low for
approximately 10µsec and then goes back high. If bit 0
(HRCFG) in HCONFIG register is 0, that is bit HREADY in
STATUS1 register is set to 1 every HRATE period right after the
harmonic calculations have started, the signal HREADY toggles
high, low and back synchronously. If bit HRCFG is 1, that is bit
HREADY in STATUS1 is set to 1 after HSTIME period, the
HREADY signal toggles high, low and back synchronously. The
HREADY signal allows fast access to the harmonic registers
without having to use HREADY interrupt in MASK1 register.
In order to facilitate the fast reading of the registers in which
the harmonic calculations are stored, a special burst registers
reading has been implemented in the serial interfaces. Please
see I2C Read Operation of Harmonic Calculations Registers
IRQ pin also goes active low. The status bit is
0
IRQ is set to high again by writing to the
0
Rev. PrE | Page 61 of 103
and SPI Read Operation of Harmonic Calculations Registers
sections for details.
Recommended approach to managing harmonic
calculations
The recommended approach to managing the ADE7880
harmonic calculations is the following:
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WAVEFORM SAMPLING MODE
The waveform samples of the current and voltage waveform,
the active, reactive, and apparent power outputs are stored
every 125 µs (8 kHz rate) into 24-bit signed registers that can be
accessed through various serial ports of the ADE7880. Table 22
provides a list of registers and their descriptions.
Table 22. Waveform Registers List
Register
IAWV
VAWV
IBWV
VBWV
ICWV
VCWV
INWV
AVA
BVA
CVA
AWATT
BWATT
CWATT
Bit 17 (DREADY) in the STATUS0 register can be used to
signal when the registers listed in Table 22 can be read using
I
enabled by setting Bit 17 (DREADY) in the MASK0 register.
See the Digital Signal Processor section for more details on
Bit DREADY.
2
C or SPI serial ports. An interrupt attached to the flag can be
Setup bit 2 (CF2DIS) in CONFIG register. Set CF2DIS bit
to 1 to use CF2/HREADY pin to signal when the harmonic
calculations have settled and are updated. The high to low
transition of HREADY signal indicates when to read the
harmonic registers. Use the burst reading mode to read the
harmonic registers as it is the most efficient way to read
them.
Choose the harmonics to be monitored by setting HX, HY
and HZ appropriately.
Select all the HCONFIG register bits.
Initialize the gain registers used in the harmonic
calculations. Leave the offset registers to 0.
Read the registers in which the harmonic information is
stored using the burst or regular reading mode at high to
low transitions of CF2/HREADY pin.
Description
Phase A current
Phase A voltage
Phase B current
Phase B voltage
Phase C current
Phase C voltage
Neutral current
Phase A apparent power
Phase B apparent power
Phase C apparent power
Phase A active power
Phase B active power
Phase C active power
ADE7880