ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 60

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
Table 23. HPFDIS register (address 0x43B6)
Bit
Location
23:0
Table 24. IPEAK register (address 0xE500)
Bit Location
23-0
24
25
26
31-27
Table 25. VPEAK register (address 0xE501)
Bit Location
23-0
24
25
26
31-27
Table 26. STATUS0 register (address 0xE502)
Bit
Location
0
1-3
4
5
6
7
8
9
10-12
13
14
15
16
17
Bit
Mnemonic
AEHF
Reserved
VAEHF
LENERGY
REVAPA
REVAPB
REVAPC
REVPSUM1
Reserved
REVPSUM2
CF1
CF2
CF3
DREADY
Bit
Mnemonic
Bit Mnemonic
VPEAKVAL[23:0]
VPPHASE[0]
VPPHASE[1]
VPPHASE[2]
Bit Mnemonic
IPEAKVAL[23:0]
IPPHASE[0]
IPPHASE[1]
IPPHASE[2]
Default
value
0
000
0
0
0
0
0
0
000
0
0
Default
value
00000000
Default value
0
0
0
0
00000
Default value
0
0
0
0
00000
Description
When this bit is set to 1, it indicates that bit 30 of any one of the total active energy registers
AWATTHR, BWATTHR, CWATTHR has changed.
These bits are always 0.
When this bit is set to 1, it indicates that bit 30 of any one of the apparent energy registers AVAHR,
BVAHR, CVAHR has changed.
When this bit is set to 1, in line energy accumulation mode, it indicates the end of an integration
over an integer number of half line cycles set in LINECYC[15:0] register.
When this bit is set to 1, it indicates that the phase A total active power has changed sign. The sign
itself is indicated in bit 0 (AWSIGN) of PHSIGN[15:0] register (see Table 36).
When this bit is set to 1, it indicates that the phase B total active power has changed sign. The sign
itself is indicated in bit 1 (BWSIGN) of PHSIGN[15:0] register (see Table 36).
When this bit is set to 1, it indicates that the phase C total active power has changed sign. The sign
itself is indicated in bit 2 (CWSIGN) of PHSIGN[15:0] register (see Table 36).
When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 data path has
changed sign. The sign itself is indicated in bit 3 (SUM1SIGN) of PHSIGN[15:0] register (see Table 36).
These bits are always 0.
When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 data path has
changed sign. The sign itself is indicated in bit 7 (SUM2SIGN) of PHSIGN[15:0] register (see Table 36).
When this bit is set to 1, it indicates a high to low transition has occurred at CF1 pin, that is an active
low pulse has been generated. The bit is set even if the CF1 output is disabled by setting bit 9
(CF1DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF1 pin is determined by bits
2-0 (CF1SEL) in CFMODE[15:0] register (see Table 34).
When this bit is set to 1, it indicates a high to low transition has occurred at CF2 pin, that is an active
low pulse has been generated. The bit is set even if the CF2 output is disabled by setting bit 10
(CF2DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF2 pin is determined by bits
5-3 (CF2SEL) in CFMODE[15:0] register (see Table 34).
When this bit is set to 1, it indicates a high to low transition has occurred at CF3 pin, that is an active
low pulse has been generated. The bit is set even if the CF3 output is disabled by setting bit 11
(CF3DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF3 pin is determined by bits
8-6 (CF3SEL) in CFMODE[15:0] register (seeTable 34).
When this bit is set to 1, it indicates that all periodical (at 8KHz rate) DSP computations have
Description
When HPFDIS=0x00000000, then all high pass filters in voltage and current channels are enabled.
When the register is set to any non zero value, all high pass filters are disabled.
These bits contain the peak value determined in the current channel.
When this bit is set to 1, phase A current generated IPEAKVAL[23:0] value.
When this bit is set to 1, phase B current generated IPEAKVAL[23:0] value.
When this bit is set to 1, phase C current generated IPEAKVAL[23:0] value.
These bits are always 0.
Description
Description
These bits contain the peak value determined in the voltage channel.
When this bit is set to 1, phase A voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, phase B voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, phase C voltage generated VPEAKVAL[23:0] value.
These bits are always 0.
Rev. PrC| Page 60 of 71
Preliminary Technical Data