ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 51

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
bits (see Figure 18 for details). HSDC can be interfaced with
SPI, SPORT (Serial Peripheral Port) or similar interfaces.
HSDC is always a master of the communication and consists in
3 pins: HSA, HSD and HSCLK. HSA represents the select
signal. It stays active low when a word is transmitted and is
usually connected to the select pin of the slave. HSD is used to
send data to the slave and is usually connected to the data input
pin of the slave. HSCLK is the serial clock line. It is generated by
the ADE7854 and is usually connected to the serial clock input
of the slave. Figure 65 and Figure 66 present details of
connections between ADE7854 HSDC and slave devices
containing SPI and SPORT interfaces.
The HSDC communication is managed by the
HSDC_CFG[7:0] register (see Table 17). It is recommended to
set HSDC_CFG register to the desired value before enabling the
port using bit 6 (HSDCEN) in CONFIG[15:0] register. In this
Table 17. HSDC_CFG register
Bit Location
0
1
2
4,3
5
7,6
Bit 2 (HGAP) introduces a gap of 7 HSCLK cycles between
packages when is set to 1. When bit HGAP is cleared to 0, the
default value, no gap is introduced between packages and the
communication time is shortest. In this case, HSIZE does not
have any influence on the communication and a bit is put on
HSD line every HSCLK high to low transition.
Bits 4,3 (HXFER[1:0]) decide how many words are transmitted.
When HXFER[1:0] is 00, the default value, then all sixteen
ADE7854
Figure 65. Connecting ADE7854 HSDC with an SPI
HSCLK
Bit Mnemonic
HCLK
HSIZE
HGAP
HXFER[1:0]
HSAPOL
HSD
HSA
0
0
0
00
0
00
Default Value
MOSI
SCK
SS
device
Description
-0: HSCLK is 8MHz
-1: HSCLK is 4MHz
-0: HSDC transmits the 32bit registers in 32bit packages, most significant bit first.
-1: HSDC transmits the 32bit registers in 8bit packages, most significant bit first.
-0: no gap is introduced between packages.
-1: a gap of 7 HCLK cycles is introduced between packages.
-00=HSDC transmits 16 registers shown in Table 21. ADE7854 billable registers
-01= HSDC transmits 6 instantaneous values of currents and voltages plus one 32-bit
word always equal to 0
-10= HSDC transmits 6 instantaneous values of phase powers plus three 32-bit words
always equal to 0
-11=reserved. If set, the ADE7854 behaves as if HXFER[1:0]=00.
-0: HSACTIVE output pin is active LOW.
-1: HSACTIVE output pin is active HIGH
Reserved. These bits do not manage any functionality.
SPI
Rev. PrC| Page 51 of 71
way, the state of various pins belonging to HSDC port do not
take levels inconsistent with the desired HSDC behaviour. After
a hardware reset or after power up, the pins MISO/HSD and
Bit 0 (HCLK) in HSDC_CFG[7:0] register determines the serial
clock frequency of the HSDC communication. When HCLK is
0, the default value, then the clock frequency is 8MHz. When
HCLK is 1, the clock frequency is 4MHz. A bit of data is
transmitted for every HSCLK high to low transition. The slave
device that receives data from HSDC samples HSD line on the
low to high transition of HSCLK.
The words may be transmitted as 32-bit packages or as 8-bit
packages. When bit 1 (HSIZE) in HSDC_CFG[7:0] register is 0,
the default value, the words are transmitted as 32-bit packages.
When bit HSIZE is 1, the registers are transmitted as 8-bit
packages. HSDC interface transmits the words with MSB first.
words are transmitted. When HXFER[1:0] is 01, then only the
words representing the instantaneous values of phase currents
and phase voltages are transmitted in the following order:
IAWV, VAWV, IBWV, VBWV, ICWV, VCWV and one 32-bit
word always equal to 0. When HXFER[1:0] is 01, then only the
instantaneous values of phase powers are transmitted in the
following order: AVA, BVA, CVA, AWATT, BWATT, CWATT,
followed by three 32-bit words always equal to 0. The value 11
SS /HSA are set high.
ADE7854
HSCLK
Figure 66. Connecting ADE7854 with a SPORT
HSD
HSA
RSCLK
DR
RFS
SPORT
ADE7854
device