ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 28

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
Note that the internal zero-crossing counter is always active. By
setting SAGLVL[23:0] register, the first sag detection result is,
therefore, not done across a full SAGCYC period. Writing to
the SAGCYC[7:0] register when the SAGLVL[23:0] is already
initialized resets the zero-crossing counter, thus ensuring that
the first sag detection result is obtained across a full SAGCYC
period.
The recommended procedure to manage sag events is the
following:
-enable SAG interrupts in MASK1[31:0] register by setting bit
16 (SAG) to 1.
-when a sag event happens, the
-STATUS1[31:0] register is read with bit 16 (SAG) set to 1.
-PHSTATUS[15:0] is read, identifying on which phase or
phases a sag event happened.
-STATUS1[31:0] register is written with bit 16 (SAG) set to 1. In
this moment, bit SAG is erased and also all bits 14,13,12
(VSPHASE[2:0]) of PHSTATUS[15:0] register.
Sag Level Set
The content of the sag level register SAGLVL[23:0] is compared
to the absolute value of the output from HPF. Writing 5,928,256
(0x5A7540) to SAGLVL register, puts the sag detection level at
full scale – see Voltage Channel ADC Chapter, so the sag event
is triggered continuously. Writing 0x00 or 0x01 puts the sag
detection level at 0, so the sag event is never triggered.
As previously stated, the serial ports of the ADE7854 work on
32, 16 or 8-bit words. Similar to the register presented in Figure
17, SAGLVL register is accessed as 32-bit registers with 8 most
significant bits padded with 0s.
Peak Detection
The ADE7854 records the maximum absolute values reached by
the voltage and current channels over a certain number of half
line cycles and stores them into the less significant 24 bits of
VPEAK[31:0] and IPEAK[31:0] 32-bit registers. PEAKCYC[7:0]
register contains the number of half line cycles used as a time
base for the measurement. It uses the zero crossing points
identified by the zero crossing detection circuit. Bits 4, 3, 2
(PEAKSEL[2:0]) in MMODE[7:0] register select on which
phases the peak measurement is done. Bit 2 selects phase A, bit
3 selects phase B and bit 4 selects phase C. Selecting more than
one phase to monitor the peak values decreases proportionally
the measurement period indicated in PEAKCYC[7:0] register
because zero crossings from more phases are involved in the
process. When a new peak value is determined, one of bits 26,
25, 24 (IPPHASE[2:0] or VPPHASE[2:0]) in IPEAK[31:0] and
VPEAK[31:0]registers is set to 1 identifying the phase that
triggered the peak detection event. For example, if a peak value
has been identified on phase A current, bit 24 (IPPHASE[0]) in
IPEAK[31:0] register is set to 1. If next time a new peak value is
measured on phase B, then bit 24 (IPPHASE[0]) of
IPEAK[31:0] is cleared to 0 and bit 25 (IPPHASE[1]) of
IRQ interrupt pin goes low.
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IPEAK[31:0] is set to 1. Figure 34 presents the composition of
IPEAK and VPEAK registers.
Figure 35 shows how the ADE7854 records the peak value on
the current channel when measurements on phases A and B are
enabled (bits PEAKSEL[2:0] in MMODE[7:0] are 011).
PEAKCYC[7:0] is set to 16, meaning that the peak
measurement cycle is 4 line periods. The maximum absolute
value of phase A is the greatest during the first 4 line periods
(PEAKCYC=16), so the maximum absolute value is written into
the less significant 24 bits of IPEAK[31:0] register and bit 24
(IPPHASE[0]) of IPEAK[31:0] register is set to 1 at the end of
the period. This bit remains 1 for the duration of the second
PEAKCYC period of 4 line cycles. The maximum absolute value
of phase B is the greatest during the second PEAKCYC period,
so the maximum absolute value is written into the less
significant 24 bits of IPEAK register and bit 25 (IPPHASE[1]) in
IPEAK register is set to 1 at the end of the period.
At the end of the peak detection period in the current channel,
bit 23 (PKI) in STATUS1[31:0] register is set to 1. If bit 23 (PKI)
in MASK1[31:0] register is set, then
low at the end of PEAKCYC period and the status bit 23 (PKI)
in STATUS1[31:0] is set to 1. In a similar way, at the end of the
Bit 24 of IPEAK
Bit 25 of IPEAK
peak detected on
Phase A
Phase B
current
current
Figure 34.Composition of IPEAK[31:0] and VPEAK[31:0] registers
phase C
Peak value written into IPEAK at
31
the end of first PEAKCYC
Figure 35. ADE7854 Peak Level Detection
Peak value written into IPEAK at
00000
the end of second PEAKCYC
Preliminary Technical Data
period
peak detected on
27
VPPHASE bits
period
IPPHASE/
26
phase B
25
24
PEAKCYC=16 period
IRQ interrupt pin is driven
23
End of first
24 bit unsigned number
1
peak detected on
phase A
Bit 24 of IPEAK
the end of first
cleared to 0 at
PEAKCYC=16 period
PEAKCYC
End of second
period
Bit 25 of IPEAK
end of second
set to 1 at the
PEAKCYC
period
0