ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 29

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
peak detection period in the voltage channel, bit 24 (PKV) in
STATUS1[31:0] register is set to 1. If bit 24 (PKV) in
MASK1[31:0] register is set, then
low at the end of PEAKCYC period and the status bit 24 (PKV)
in STATUS1[31:0] is set to 1. To find the phase that triggered
the interrupt, one of IPEAK[31:0] or VPEAK[31:0] registers is
read immediately after reading STATUS1[31:0]. Then the
status bits are cleared and
STATUS1[31:0] register with the status bit set to 1.
Note that the internal zero-crossing counter is always active. By
setting bits 4, 3, 2 (PEAKSEL[2:0]) in MMODE[7:0] register, the
first peak detection result is, therefore, not done across a full
PEAKCYC period. Writing to the PEAKCYC[7:0] register when
the PEAKSEL[2:0] bits are set resets the zero-crossing counter,
thus ensuring that the first peak detection result is obtained
across a full PEAKCYC period.
Overvoltage and Overcurrent Detection
The ADE7854 detects when the instantaneous absolute value
measured on the voltage and current channels becomes greater
than thresholds set in OVLVL[23:0] and OILVL[23:0] 24-bit
unsigned registers. If bit 18 (OV) in MASK1[31:0] register is
set,
event. There are two status flags set when
driven low: bit 18 (OV) in STATUS1[31:0] register and one of
bits 11, 10, 9 (OVPHASE[2:0]) in PHSTATUS[15:0] register
identifying the phase that generated the overvoltage. The status
bit 18 (OV) in STATUS1[31:0] register and all bits 11, 10, 9
(OVPHASE[2:0]) in PHSTATUS[15:0] register are cleared and
with the status bit set to 1. Figure 36 presents overvoltage
detection in phase A voltage. Whenever the absolute
instantaneous value of the voltage goes above the threshold
from OVLVL[23:0] register, bit 18 (OV) in STATUS1[31:0] and
bit 9 (OVPHASE[0]) in PHSTATUS[15:0] registers are set to 1.
The bit 18 (OV) of STATUS1[31:0] register and bit 9
(OVPHASE[0]) in PHSTATUS[15:0] register are cancelled
when STATUS1 register is written with bit 18 (OV) set to 1.
IRQ pin is set back high by writing STATUS1[31:0] register
1
IRQ interrupt pin is driven low in case of an overvoltage
1
IRQ pin is set back high by writing
1
IRQ interrupt pin is driven
1
IRQ interrupt pin is
1
Rev. PrC| Page 29 of 71
The recommended procedure to manage overvoltage events is
the following:
-enable OV interrupts in MASK1[31:0] register by setting bit 18
(OV) to 1.
-when an overvoltage event happens, the
goes low.
-STATUS1[31:0] register is read with bit 18 (OV) set to 1.
-PHSTATUS[15:0] is read, identifying on which phase or
phases an overvoltage event happened.
-STATUS1[31:0] register is written with bit 18 (OV) set to 1. In
this moment, bit OV is erased and also all bits 11, 10, 9
(OVPHASE[2:0]) of PHSTATUS[15:0] register.
In case of an overcurrent event, if bit 17 (OI) in MASK1[31:0]
register is set,
moment, bit 17 (OI) in STATUS1[31:0] register and one of bits
5,4,3 (OIPHASE[2:0]) in PHSTATUS[15:0] register identifying
the phase that generated the interrupt are set. To find the phase
that triggered the interrupt, PHSTATUS[15:0] register is read
immediately after reading STATUS1[31:0]. Then the status bit
17 (OI) in STATUS1[31:0] register and bits 5,4,3
(OIPHASE[2:0]) in PHSTATUS[15:0] register are cleared and
with the status bit set to 1. The process is similar with the
overvoltage detection.
Overvoltage and Overcurrent Level Set
The content of the overvoltage OVLVL[23:0] and overcurrent
OILVL[23:0] 24-bit unsigned registers is compared to the
absolute value of the voltage and current channels. The
maximum value of these registers is the maximum value of the
HPF outputs: +5,928,256 (0x5A7540). When OVLVL or OILVL
are equal to this value, the overvoltage or overcurrent
IRQ pin is set back high by writing STATUS1[31:0] register
Bit 9 (OVPHASE)
of PHSTATUS
1
Bit 18 (OV) of
OVLVL[23:0]
Voltage Channel
STATUS1
Phase A
Figure 36. ADE7854 Overvoltage Detection
IRQ interrupt pin is driven low. In the same
1
Overvoltage
detected
IRQ interrupt pin
1
cancelled by a write
STATUS1[18] and
of STATUS1 with
PHSTATUS[9]
ADE7854
OV bit set