ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 35

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Active Power Gain Calibration
Note that the average active power result from the LPF2 output
in each phase can be scaled by ±100% by writing to the phase’s
watt gain 24-bit register (AWGAIN[23:0], BWGAIN[23:0],
CWGAIN[23:0]). xWGAIN, x=A,B,C registers are placed in
each phase of the total active power data path. The watt gain
registers are twos complement, signed registers and have a
resolution of 2
the function of the watt gain registers.
The output is scaled by −50% by writing 0xC00000 to the watt
gain registers and increased by +50% by writing 0x400000 to
them. These registers can be used to calibrate the active power
(or energy) calculation in the ADE7854 for each phase.
As previously stated, the serial ports of the ADE7854 work on
32, 16 or 8-bit words and the DSP works on 28 bits. Similar to
registers presented in Figure 16, AWGAIN, BWGAIN,
CWGAIN 24-bit signed registers are accessed as 32-bit registers
with 4 most significant bits padded with 0s and sign extended
to 28 bits.
Active Power Offset Calibration
The ADE7854 also incorporates a watt offset 24-bit register on
each phase and on each active power. AWATTOS[23:0],
BWATTOS[23:0], and CWATTOS[23:0] registers compensate
the offsets in the total active power calculations. These are
signed twos complement, 24-bit registers that are used to
remove offsets in the active power calculations. An offset can
exist in the power calculation due to crosstalk between channels
on the PCB or in the chip itself. The offset calibration allows the
contents of the active power register to be maintained at 0 when
no power is being consumed. One LSB in the active power
offset register is equivalent to 1 LSB in the active power
multiplier output. With full scale current and voltage inputs, the
LPF2 output is PMAX=33,516,139. At -80dB down from the
full scale (active power scaled down 10
active power offset register represents 0.032% of PMAX.
As previously stated, the serial ports of the ADE7854 work on
32, 16 or 8-bit words and the DSP works on 28 bits. Similar to
registers presented in Figure 16, AWATTOS, BWATTOS,
CWATTOS 24-bit signed registers are accessed as 32-bit
registers with 4 most significant bits padded with 0s and sign
extended to 28 bits.
Sign of Active Power Calculation
Note that the average active power is a signed calculation. If the
phase difference between the current and voltage waveform is
more than 90°, the average power becomes negative. Negative
power indicates that energy is being injected back on the grid.
The ADE7854 has a sign detection circuitry for total active
Average
LPF
2
Output
Power
-23
×
/LSB. Equation
Data
⎛
⎜ ⎜
⎝
1
+
=
Watt
Gain
2
23
(18
Re
) describes mathematically
gister
4
times), one LSB of the
⎞
⎟ ⎟
⎠
Rev. PrC| Page 35 of 71
(18)
power calculations. As will be seen in the Active Energy
Calculation section, the active energy accumulation is
performed in two stages. Every time a sign change is detected in
the energy accumulation at the end of the first stage, that is after
the energy accumulated into the 48 bit accumulator reaches
WTHR[47:0] threshold, a dedicated interrupt is triggered. The
sign of each phase active power may be read in PHSIGN[15:0]
register.
Bits 8, 7, 6 (REVAPC, REVAPB and respectively REVAPA) in
STATUS0[31:0] are set when a sign change occurs in the total
active power.
Bits 2, 1, 0 (CWSIGN, BWSIGN and respectively AWSIGN) in
PHSIGN[15:0] register are set simultaneously with REVAPC,
REVAPB and REVAPA bits. They indicate the sign of the power.
When they are 0, the total active power is positive. When they
are 1, the total active power is negative.
Interrupts attached to the bits 8, 7, 6 (REVAPC, REVAPB and
respectively REVAPA) in STATUS0[31:0] register may be
enabled by setting bits 8,7,6 in MASK0[31:0] register. If
enabled, the
whenever a change of sign occurs. To find the phase that
triggered the interrupt, PHSIGN[15:0] register is read
immediately after reading STATUS0[31:0]. Then the status bit is
cleared and
register with the corresponding bit set to 1.
Active Energy Calculation
As previously stated, power is defined as the rate of energy flow.
This relationship can be expressed mathematically as
Conversely, Energy is given as the integral of power.
Total active energy accumulation is signed. Negative energy is
subtracted from the active energy contents.
The ADE7854 achieves the integration of the active power
signal in two stages (see Figure 45). The process is identical for
both total and fundamental active powers. The first stage is
done inside the DSP: every 125μsec (8KHz frequency), the
instantaneous phase total or fundamental active power is
accumulated into an internal 56-bit register. When a threshold
is reached, a pulse is generated at processor port and the
threshold is subtracted from the internal register. The sign of
the energy in this moment is considered the sign of the active
power (see Sign of Active Power Calculation section for details).
The second stage is done outside the DSP and consists in
accumulating the pulses generated by the processor into
internal 32-bit accumulation registers. The content of these
registers is transferred to watt-hr registers xWATTHR[31:0],
x=A,B,C when these registers are accessed. AWATTHR[31:0],
Power =
Energy
=
dEnergy
∫
p
IRQ pin is set back high by writing STATUS0
dt
( )
IRQ pin is set low and the status bit is set to 1
t
dt
0
0
ADE7854
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