saa7146a NXP Semiconductors, saa7146a Datasheet - Page 27

• Manufacturer Part Number: saa7146a
• Description: Multimedia Bridge, High Performance Scaler And Pci Circuit Spci
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 10 Main control register 1
2004 Aug 25
OFFSET
Mask word
FC
Control word
FC
(HEX)
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
M15 to M00
MRST_N
ERPS1
ERPS0
EDP
EVP
EAP
EI2C
TR_E_DEBI
TR_E_1
TR_E_2
TR_E_3
TR_E_A2_OUT 3
TR_E_A2_IN
TR_E_A1_OUT 1
TR_E_A1_IN
NAME
31 to 16 RW
15
14
13
12
11
10
9
8
7
6
5
4
2
0
BIT
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
TYPE
16-bit mask word for bit-selective writes to the control word; when
read these bits always return logic 0
Master Reset Not: this is the master reset for the SAA7146A. Writing
a logic 0 to this bit will reset the SAA7146A to the same state as after
a power-on reset. When read this bit always returns a logic 0.
reserved: when read this bit always returns a logic 0
Enable Register Program Sequencer Task 1: if ERPS1 = 1, then
any RPS Task 1 action is enabled. If ERPS1 = 0, then RPS Task 1
action does not fetch any more commands.
Enable Register Program Sequencer Task 0: if ERPS0 = 1, then
any RPS Task 0 action is enabled. If ERPS0 = 0, then RPS Task 0
action does not fetch any more commands.
Enable DEBI Port pins: if EDP = 0, all pins of the DEBI port are set
to 3-state. If EDP = 1, then the function of all pins at the DEBI port is
as programmed via the DEBI registers.
Enable Real Time Video Ports pins: if EVP = 0, all 24 pins of the
real time video interface (DD1 port) are 3-stated. If EVP = 1, then the
function of all pins at the real time video interface (DD1 port) is as
programmed by the scaler register; see Table 66.
Enable Audio Port pins: if EAP = 0, all 14 pins of the audio interface
port are set to 3-state. If EAP = 1, then the function of all pins at the
audio interface is as programmed in Section 7.16.3.
Enable I
interface port are set to 3-state. If EI2C = 1, then the I
is enabled and will function as programmed in Section 7.17.2.
Transfer Enable bit of the DEBI.
Transfer enable bit of video Channel 1: if set this channel is included
in the internal arbitration scheme. If not set, this channel will be
ignored and no transfer will start using this FIFO.
Transfer Enable bit of video channel 2: if set this channel is included in
the internal arbitration scheme. If not set, this channel will be ignored
and no transfer will start using this FIFO.
Transfer Enable bit of video channel 3: if set this channel is included in
the internal arbitration scheme. If not set, this channel will be ignored
and no transfer will start using this FIFO.
Transfer Enable bit of audio channel 2 out
Transfer Enable bit of audio channel 2 in
Transfer Enable bit of audio channel 1 out
Transfer Enable bit of audio channel 1 in
2
C-bus Port pins: if EI2C = 0, then both pins of the I
27
DESCRIPTION
Product specification
SAA7146A
2
C-bus interface
2
C-bus