saa7146a NXP Semiconductors, saa7146a Datasheet - Page 112

• Manufacturer Part Number: saa7146a
• Description: Multimedia Bridge, High Performance Scaler And Pci Circuit Spci
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.16.5
The configuration parameters are selected using two configuration registers, ACON1 and ACON2.
The ACON1 register is locally buffered. The download from the shadow register into the working register is performed
when a DMA protection address is reached or immediately when both interfaces are not active (switched off, initial state).
Table 103Audio Configuration Register 1 (ACON1)
Table 104Audio Configuration Register 2 (ACON2)
2004 Aug 25
F4
F8
OFFSET
OFFSET
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
(HEX)
(HEX)
A
UDIO CONFIGURATION
AUDIO_MODE [2:0]
MAXLEVEL [6:0]
A1_SWAP
A2_SWAP
WS0_CTRL [1:0]
WS0_SYNC [1:0]
WS1_CTRL [1:0]
WS1_SYNC [1:0]
WS2_CTRL [1:0]
WS2_SYNC [1:0]
WS3_CTRL [1:0]
WS3_SYNC [1:0]
WS4_CTRL [1:0]
WS4_SYNC [1:0]
A1_CLKSRC [4:0]
A2_CLKSRC [4:0]
INVERT_BCLK1
INVERT_BCLK2
BCLK1_OEN
BCLK2_OEN
NAME
NAME
21
20
31 to 29
28 to 22
19 and 18
17 and 16
15 and 14
13 and 12
11 and 10
9 and 8
7 and 6
5 and 4
3 and 2
1 and 0
31 to 27
26 to 22
21
20
19
18
BIT
BIT
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
TYPE
TYPE
defines interface activation and combination
defines the maximum allowed absolute value for the most
significant byte of an audio sample
defines if input (captured) data is stuffed in little-endian or
big-endian format for A1 (4-byte swap if set)
defines if input (captured) data is stuffed in little-endian or
big-endian format for A2 (4-byte swap if set)
function control for WS0 line
pulse position and width control for WS0 line
function control for WS1 line
pulse position and width control for WS1 line
function control for WS2 line
pulse position and width control for WS2 line
function control for WS3 line
pulse position and width control for WS3 line
function control for WS4 line
pulse position and width control for WS4 line
defines the bit clock source for A1
defines the bit clock source for A2
input or output BCLK1 with inverted polarity
input or output BCLK2 with inverted polarity
output enable BCLK1 (active LOW)
output enable BCLK2 (active LOW)
112
DESCRIPTION
DESCRIPTION
Product specification
SAA7146A