adsp-21991 Analog Devices, Inc., adsp-21991 Datasheet - Page 7

• Manufacturer Part Number: adsp-21991
• Description: Mixed Signal Dsp Controller
• Manufacturer: Analog Devices, Inc.

for position sensor feedback; two adjustable frequency auxiliary
PWM outputs, 16 lines of digital I/O; a 16-bit watchdog timer;
three general-purpose timers, and an interrupt controller that
manages all peripheral interrupts. Finally, the ADSP-21991
contains an integrated power-on-reset (POR) circuit that can be
used to generate the required reset signal for device power-on.
The ADSP-21991 has an external memory interface that is
shared by the DSP core, the DMA controller, and DMA capable
peripherals, which include the ADC, SPORT, and SPI commu-
nication ports. The external port consists of a 16-bit data bus, a
20-bit address bus, and control signals. The data bus is config-
urable to provide an 8- or 16-bit interface to external memory.
Support for word packing lets the DSP access 16- or 24-bit words
from external memory regardless of the external data bus width.
The memory DMA controller lets the ADSP-21991 move data
and instructions from between memory spaces: internal-to-
external, internal-to-internal, and external-to- external. On-chip
peripherals can also use this controller for DMA transfers.
The embedded ADSP-219x core can respond to up to seventeen
interrupts at any given time: three internal (stack, emulator
kernel, and power-down), two external (emulator and reset), and
twelve user defined (peripherals) interrupts. Programmers assign
each of the 32 peripheral interrupt requests to one of the 12 user
defined interrupts. These assignments determine the priority of
each peripheral for interrupt service.
The following sections provide a functional overview of the
ADSP-21991 peripherals.
Serial Peripheral Interface (SPI) Port
The Serial Peripheral Interface (SPI) Port provides functionality
for a generic configurable serial port interface based on the SPI
standard, which enables the DSP to communicate with multiple
SPI compatible devices. Key features of the SPI port are:
• Interface to host microcontroller or serial EEPROM
• Master or slave operation (3-wire interface MISO, MOSI,
• Data rates to HCLK 4 (16-bit baud rate selector)
• 8- or 16-bit transfer
• Programmable clock phase and polarity
• Broadcast Mode – 1 master, multiple slaves
• DMA capability and dedicated interrupts
• PF0 can be used as slave select input line
• PF7–1 can be used as external slave select output
SPI is a 3 wire interface consisting of 2 data pins (MOSI and
MISO), one clock pin (SCK), and a single Slave Select input
(SPISS) that is multiplexed with the PF0 Flag IO line and seven
Slave Select outputs (SPISEL1 to SPISEL7) that are multiplexed
with the PF1 to PF7 Flag IO lines. The SPISS input is used to
select the ADSP-21991 as a slave to an external master. The
SPISEL1 to SPISEL7 outputs can be used by the ADSP-21991
(acting as a master) to select/enable up to seven external slaves
in an multi device SPI configuration. In a multimaster or a multi-
device configuration, all MOSI pins are tied together, all MISO
pins are tied together, and all SCK pins are tied together.
REV. 0
SCK)
–7–
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on the serial data line.
The serial clock line synchronizes the shifting and sampling of
data on the serial data line.
In master mode, the DSP core performs the following sequence
to set up and initiate SPI transfers:
1. Enables and configures the SPI port operation (data size,
2. Selects the target SPI slave with the SPISELx output pin
3. Defines one or more DMA descriptors in Page 0 of I/O
4. Enables the SPI DMA engine and specifies transfer
5. In non DMA mode only, reads or writes the SPI port
The SCK line generates the programmed clock pulses for simul-
taneously shifting data out on MOSI and shifting data in on
MISO. In DMA mode only, transfers continue until the SPI
DMA word count transitions from 1 to 0.
In slave mode, the DSP core performs the following sequence to
set up the SPI port to receive data from a master transmitter:
1. Enables and configures the SPI slave port to match the
2. Defines and generates a receive DMA descriptor in
3. Enables the SPI DMA engine for a receive access
4. Starts receiving the data on the appropriate SCK edges
In DMA mode only, reception continues until the SPI DMA
word count transitions from 1 to 0. The DSP core could
continue, by queuing up the next DMA descriptor.
A slave mode transmit operation is similar, except the DSP core
specifies the data buffer in memory space from which to transmit
data, generates and relinquishes control of the transmit DMA
descriptor, and begins filling the SPI port data buffer. If the SPI
controller is not ready on time to transmit, it can transmit a “zero”
word.
DSP Serial Port (SPORT)
The ADSP-21991 incorporates a complete synchronous serial
port (SPORT) for serial and multiprocessor communications.
The SPORT supports the following features:
• Bidirectional: the SPORT has independent transmit and
• Double buffered: the SPORT section (both receive and
receive sections.
transmit) has a data register for transferring data words
to and from other parts of the processor and a register for
shifting data in or out. The double buffering provides
additional time to service the SPORT.
and transfer format).
(reconfigured Programmable Flag pin).
memory space (optional in DMA mode only).
direction (optional in DMA mode only).
receive or transmit data buffer.
operation parameters set up on the master (data size and
transfer format) SPI transmitter.
Page 0 of memory space to interrupt at the end of the
data transfer (optional in DMA mode only).
(optional in DMA mode only).
after receiving an SPI chip select on the SPISS input pin
(reconfigured Programmable Flag pin) from a master
ADSP-21991