adsp-21991 Analog Devices, Inc., adsp-21991 Datasheet - Page 5

• Manufacturer Part Number: adsp-21991
• Description: Mixed Signal Dsp Controller
• Manufacturer: Analog Devices, Inc.

contain the configuration registers for the peripherals. Both the
ADSP-219x core and DMA capable peripherals can access the
entire memory map of the DSP.
NOTE: The physical external memory addresses are limited by
20 address lines, and are determined by the external data width
and packing of the external memory space. The Strobe signals
(MS3-0) can be programmed to allow the user to change starting
page addresses at run time.
Internal (On-Chip) Memory
The unified program and data memory space of the ADSP-21991
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA, and DMA buses. The DSP uses slightly
different mechanisms to generate a 24-bit address for each bus.
The DSP has three functions that support access to the full
memory map.
• The DAGs generate 24-bit addresses for data fetches from
• The program sequencer generates the addresses for
REV. 0
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG DMPGx register to the
appropriate memory page. The DMPG1 register is also
used as a page register when accessing external memory.
The program must set DMPG1 accordingly, when
accessing data variables in external memory. A “C”
program macro is provided for setting this register.
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
0x00 0000
0x00 3FFF
0x00 4000
0x00 7FFF
0x00 8000
0x00 9FFF
0x00 A000
0x00 FFFF
0x01 0000
0x40 0000
0x80 0000
0xC0 0000
0xFF 0000
0xFF 0FFF
0xFF 1000
0xFF FFFF
BLOCK 0: 16K
BLOCK 1: 16K
Figure 2. Core Memory Map at Reset
BLOCK 2: 8K
EXTERNAL MEMORY (4M)
EXTERNAL MEMORY (4M)
EXTERNAL MEMORY
EXTERNAL MEMORY
BLOCK 3: 4K
RESERVED (24K)
UNUSED ON-CHIP
MEMORY (60K)
(4M–64K)
(4M–64K)
PM ROM
16-BIT DM RAM
24-BIT PM RAM
24-BIT PM RAM
24-BIT
(OFF-CHIP) MS0
PAGES 1 TO 63 BANK 0
PAGES 64 TO 127 BANK 1
(OFF-CHIP) MS1
PAGES 128 TO 191 BANK 2
(OFF-CHIP) MS2
PAGES 192 TO 254 BANK 3
(OFF-CHIP) MS3
PAGE 0 (64K) ON-CHIP
(0 WAIT STATE)
PAGE 255
(INCLUDES ON-CHIP BOOT ROM)
–5–
• For indirect jumps and calls that use a 16-bit DAG
The ADSP-21991 has 4K word of on-chip ROM that holds boot
routines. The DSP starts executing instructions from the on-chip
boot ROM, which starts the boot process.
on Page 13.
the DSP memory space map, starting at address 0xFF0000.
External (Off-Chip) Memory
Each of the off-chip memory spaces of the ADSP-21991 has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write wait counts, wait state completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
the external memory access strobe widths.
Page 12.
• External memory space (MS3–0 pins)
• I/O memory space (IOMS pin)
• Boot memory space (BMS pin)
All of these off-chip memory spaces are accessible through the
External Port, which can be configured for 8-bit or 16-bit data
widths.
External Memory Space
External memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0 con-
taining pages 1 to 63, Bank1 containing pages 64 to 127, Bank2
containing pages 128 to 191, and Bank3 containing pages 192 to
254. The MS3-0 memory bank pins select Banks 3-0, respec-
tively. Both the ADSP-219x core and DMA capable peripherals
can access the DSP external memory space.
All accesses to external memory are managed by the External
Memory Interface Unit (EMI).
I/O Memory Space
The ADSP-21991 supports an additional external memory
called I/O memory space. The IO space consists of 256 pages,
each containing 1024 addresses. This space is designed to
support simple connections to peripherals (such as data convert-
ers and external registers) or to bus interface ASIC data registers.
The first 32K addresses (IO pages 0 to 31) are reserved for
on-chip peripherals. The upper 224K addresses (IO pages 32 to
calls, and loops on the 24-bit program counter (PC). In
direct addressing instructions (two word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer IJPG register to the
appropriate memory page.
The off-chip memory spaces are:
The on-chip boot ROM is located on Page 255 in
ADSP-21991
See Clock Signals on
See Booting Modes